JPS639659U - - Google Patents

Info

Publication number
JPS639659U
JPS639659U JP10081286U JP10081286U JPS639659U JP S639659 U JPS639659 U JP S639659U JP 10081286 U JP10081286 U JP 10081286U JP 10081286 U JP10081286 U JP 10081286U JP S639659 U JPS639659 U JP S639659U
Authority
JP
Japan
Prior art keywords
latch
circuit
buffer circuit
latch circuit
bit unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10081286U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10081286U priority Critical patent/JPS639659U/ja
Publication of JPS639659U publication Critical patent/JPS639659U/ja
Pending legal-status Critical Current

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  • Bus Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の実施例を示すブロツク図、
第2図は従来例を示すブロツク図である。 図中、L,L……ラツチ回路、B,B
……バツフア回路。
Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is a block diagram showing a conventional example. In the figure, L 1 , L 4 ... latch circuit, B 1 , B 4
...Batsuhua circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数ビツトバスを数分割したビツト単位ごとに
ラツチするために備えたラツチ回路群と、前記複
数ビツトバスの上位もしくは下位に相当するビツ
ト単位データをオンオフする第1のバツフア回路
と、そのビツト単位データを一時ラツチするラツ
チ回路と、そのラツチ回路の出力をオンオフする
第2のバツフア回路とを備え、前記ラツチ回路群
の内上位もしくは下位に相当するラツチ回路に前
記第1もしくは第2のバツフア回路の出力をラツ
チするように構成したことを特徴とするデータ送
出回路。
A group of latch circuits provided to latch each bit unit obtained by dividing a multi-bit bus into several parts, a first buffer circuit for turning on/off bit unit data corresponding to the upper or lower part of the plural bit bus, and a first buffer circuit for temporarily latching the bit unit data. The latch circuit includes a latch circuit that latches, and a second buffer circuit that turns on and off the output of the latch circuit, and the output of the first or second buffer circuit is provided to the latch circuit corresponding to the higher or lower level of the latch circuit group. A data transmission circuit characterized in that it is configured to latch.
JP10081286U 1986-07-02 1986-07-02 Pending JPS639659U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10081286U JPS639659U (en) 1986-07-02 1986-07-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10081286U JPS639659U (en) 1986-07-02 1986-07-02

Publications (1)

Publication Number Publication Date
JPS639659U true JPS639659U (en) 1988-01-22

Family

ID=30970976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10081286U Pending JPS639659U (en) 1986-07-02 1986-07-02

Country Status (1)

Country Link
JP (1) JPS639659U (en)

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