JPS63171843U - - Google Patents
Info
- Publication number
- JPS63171843U JPS63171843U JP6397087U JP6397087U JPS63171843U JP S63171843 U JPS63171843 U JP S63171843U JP 6397087 U JP6397087 U JP 6397087U JP 6397087 U JP6397087 U JP 6397087U JP S63171843 U JPS63171843 U JP S63171843U
- Authority
- JP
- Japan
- Prior art keywords
- output
- microprocessor
- highest priority
- terminal
- priority interrupt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Description
第１図は、ワンチツプマイクロプロセツサの概
略図、第２図はアウトプツトコンペア手段を示す
ブロツク図、第３図ａ，ｂはマイクロプロセツサ
で実行される割り込み処理のフローチヤート、第
４図はＯＣ端子の出力と割り込み処理のタイムチ
ヤート、第５図は複数の出力端子からのパルス信
号出力のフローチヤートである。
１……マイクロプロセツサ、２……アウトプツ
トコンペア手段の出力端子（ＯＣ端子）、３……
最優先の割り込み手段の入力端子（ＮＭｉ端子）
、５〜７……出力端子。
FIG. 1 is a schematic diagram of a one-chip microprocessor, FIG. 2 is a block diagram showing the output comparison means, FIGS. 3a and b are a flowchart of interrupt processing executed by the microprocessor, and FIG. 4 is a time chart of the output of the OC terminal and interrupt processing, and FIG. 5 is a flow chart of pulse signal output from a plurality of output terminals. 1...Microprocessor, 2...Output terminal (OC terminal) of output comparison means, 3...
Input terminal of highest priority interrupt method (NMi terminal)
, 5 to 7...output terminals.
Claims (1)
手段とを備えるとともに、信号を出力する複数の
出力端子とを備えたマイクロプロセツサにおいて
、アウトプツトコンペア手段の出力端子と最優先
の割り込み手段の入力端子とを接続したことを特
徴とするマイクロプロセツサ。 In a microprocessor that is equipped with an output compare means, a highest priority interrupt means, and a plurality of output terminals for outputting signals, the output terminal of the output compare means and the input terminal of the highest priority interrupt means are connected. A microprocessor characterized by being connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6397087U JPS63171843U (en) | 1987-04-30 | 1987-04-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6397087U JPS63171843U (en) | 1987-04-30 | 1987-04-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63171843U true JPS63171843U (en) | 1988-11-08 |
Family
ID=30899697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6397087U Pending JPS63171843U (en) | 1987-04-30 | 1987-04-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63171843U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5755453A (en) * | 1980-09-19 | 1982-04-02 | Nec Corp | Timer device |
-
1987
- 1987-04-30 JP JP6397087U patent/JPS63171843U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5755453A (en) * | 1980-09-19 | 1982-04-02 | Nec Corp | Timer device |