JPS6335138U - - Google Patents
Info
- Publication number
- JPS6335138U JPS6335138U JP12682986U JP12682986U JPS6335138U JP S6335138 U JPS6335138 U JP S6335138U JP 12682986 U JP12682986 U JP 12682986U JP 12682986 U JP12682986 U JP 12682986U JP S6335138 U JPS6335138 U JP S6335138U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- outputs
- reference value
- controller
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案のデジタル比較回路のブロツク
系統図、第２図は従来のデジタル比較回路のブロ
ツク系統図である。
１，１０……コントローラ、２……データバツ
フア、３，３０……比較器、２０……第１データ
バツフア、４０……アナログデジタル変換器（Ａ
ＤＣ）、５０……インバータ、６０……第２デー
タバツフア。
FIG. 1 is a block system diagram of a digital comparison circuit of the present invention, and FIG. 2 is a block system diagram of a conventional digital comparison circuit. 1, 10... Controller, 2... Data buffer, 3, 30... Comparator, 20... First data buffer, 40... Analog-to-digital converter (A
DC), 50...inverter, 60...second data buffer.
Claims (1)
方の入力端にデジタル比較値が供給され、これ等
２入力の比較結果を出力する比較器を具備するデ
ジタル比較回路において、前記デジタル基準値は
、コントローラで動作制御され且つこのコントロ
ーラによつて与えられたデータを固定基準モード
の第１デジタル基準値として出力する第１データ
バツフアと、リアルタイムに変化するアナログ信
号を連続的にデジタル変換して出力するアナログ
デジタル変換器からのデジタル信号を入力して前
記第１データバツフアと逆動作となるように前記
コントローラで動作制御されるリアルタイムで変
化する第２デジタル基準値として出力する第２デ
ータバツフアとから得るようにしたことを特徴と
するデジタル比較回路。 In a digital comparison circuit comprising a comparator that is supplied with a digital reference value at one input terminal and a digital comparison value at the other input terminal and outputs a comparison result of these two inputs, the digital reference value is A first data buffer whose operation is controlled by a controller and which outputs data given by the controller as a first digital reference value in a fixed reference mode; and an analog buffer which continuously converts analog signals that change in real time into digital and outputs the data. and a second data buffer that receives a digital signal from a digital converter and outputs it as a second digital reference value that changes in real time and is controlled by the controller so as to operate in the opposite manner to the first data buffer. A digital comparison circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12682986U JPS6335138U (en) | 1986-08-20 | 1986-08-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12682986U JPS6335138U (en) | 1986-08-20 | 1986-08-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6335138U true JPS6335138U (en) | 1988-03-07 |
Family
ID=31021008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12682986U Pending JPS6335138U (en) | 1986-08-20 | 1986-08-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6335138U (en) |
-
1986
- 1986-08-20 JP JP12682986U patent/JPS6335138U/ja active Pending