JPS6331626U - - Google Patents
Info
- Publication number
- JPS6331626U JPS6331626U JP12412086U JP12412086U JPS6331626U JP S6331626 U JPS6331626 U JP S6331626U JP 12412086 U JP12412086 U JP 12412086U JP 12412086 U JP12412086 U JP 12412086U JP S6331626 U JPS6331626 U JP S6331626U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- signal
- analog
- comparator
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第1図は本考案の具体的な実施例を示すアナロ
グ・デジタル変換器のブロツク線図、第2図は第
1図の動作を示すフローシート、第3図は従来の
アナログ・デジタル変換器の構成を示すブロツク
線図、第4図及び第5図の従来の技術の説明に供
する図である。
1……比較器(第1比較器)、2,20……プ
ロセツサ、3……デジタル・アナログ変換器(D
AC)、5……データレジスタ、6……サンプル
ホールド回路、7……演算回路、8……第2比較
器。
Fig. 1 is a block diagram of an analog-to-digital converter showing a specific embodiment of the present invention, Fig. 2 is a flow sheet showing the operation of Fig. 1, and Fig. 3 is a diagram of a conventional analog-to-digital converter. FIG. 5 is a block diagram showing the configuration and a diagram for explaining the conventional technology of FIGS. 4 and 5; FIG. 1... Comparator (first comparator), 2, 20... Processor, 3... Digital-to-analog converter (D
AC), 5...data register, 6...sample hold circuit, 7...arithmetic circuit, 8...second comparator.
Claims (1)
器と、該第1比較器からの第1比較信号を入力す
る逐次比較機能を有するプロセツサと、該プロセ
ツサから逐次出力されるデジタルデータを一次保
持するデータレジスタと、該データレジスタから
のデジタル信号出力をアナログ信号に変換して前
記第1比較器の他方に出力するデジタル・アナロ
グ変換器と、該デジタル・アナログ変換器からの
アナログ信号を一時保持するサンプルホールド回
路と、該サンプルホールド回路からのサンプルホ
ールド信号と前記入力アナログ信号とを入力して
加算演算又は減算演算する演算回路と、該演算回
路の1倍又はN倍の値の出力値を一方から入力し
前記デジタル・アナログ変換器からのアナログ信
号の1/N倍又は1倍の値を他方から入力し前記
プロセツサに第2比較信号を出力する第2比較器
とを具備したことを特徴とするアナログ・デジタ
ル変換器。 A first comparator that receives an input analog signal as one input, a processor that has a successive approximation function that inputs the first comparison signal from the first comparator, and that temporarily holds digital data sequentially output from the processor. a data register; a digital-to-analog converter that converts a digital signal output from the data register into an analog signal and outputs it to the other of the first comparators; and temporarily holds the analog signal from the digital-to-analog converter. a sample and hold circuit; an arithmetic circuit that inputs the sample and hold signal from the sample and hold circuit and the input analog signal and performs an addition or subtraction operation; and a second comparator that inputs from the other side a value 1/N times or 1 times the analog signal from the digital-to-analog converter and outputs a second comparison signal to the processor. Analog to digital converter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12412086U JPH048672Y2 (en) | 1986-08-13 | 1986-08-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12412086U JPH048672Y2 (en) | 1986-08-13 | 1986-08-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6331626U true JPS6331626U (en) | 1988-03-01 |
JPH048672Y2 JPH048672Y2 (en) | 1992-03-04 |
Family
ID=31015842
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12412086U Expired JPH048672Y2 (en) | 1986-08-13 | 1986-08-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH048672Y2 (en) |
-
1986
- 1986-08-13 JP JP12412086U patent/JPH048672Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPH048672Y2 (en) | 1992-03-04 |
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