JPS6331626U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an analog-to-digital converter showing a specific embodiment of the present invention, Fig. 2 is a flow sheet showing the operation of Fig. 1, and Fig. 3 is a diagram of a conventional analog-to-digital converter. FIG. 5 is a block diagram showing the configuration and a diagram for explaining the conventional technology of FIGS. 4 and 5; FIG. 1... Comparator (first comparator), 2, 20... Processor, 3... Digital-to-analog converter (D
AC), 5...data register, 6...sample hold circuit, 7...arithmetic circuit, 8...second comparator.

Claims (1)

[Scope of utility model registration request] A first comparator that receives an input analog signal as one input, a processor that has a successive approximation function that inputs the first comparison signal from the first comparator, and that temporarily holds digital data sequentially output from the processor. a data register; a digital-to-analog converter that converts a digital signal output from the data register into an analog signal and outputs it to the other of the first comparators; and temporarily holds the analog signal from the digital-to-analog converter. a sample and hold circuit; an arithmetic circuit that inputs the sample and hold signal from the sample and hold circuit and the input analog signal and performs an addition or subtraction operation; and a second comparator that inputs from the other side a value 1/N times or 1 times the analog signal from the digital-to-analog converter and outputs a second comparison signal to the processor. Analog to digital converter.