JPS6293835U - - Google Patents
Info
- Publication number
- JPS6293835U JPS6293835U JP18295485U JP18295485U JPS6293835U JP S6293835 U JPS6293835 U JP S6293835U JP 18295485 U JP18295485 U JP 18295485U JP 18295485 U JP18295485 U JP 18295485U JP S6293835 U JPS6293835 U JP S6293835U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- analog
- signals
- analog signals
- multiple channels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000000295 complement effect Effects 0.000 claims 1
- 238000011144 upstream manufacturing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000009182 swimming Effects 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例よりなるＤＡ変換回
路のブロツク図、第２図はデイジタル信号処理回
路６の回路図、第３図は位相差の周波数特性曲線
、第４図は従来例よりなるＤＡ変換回路のブロツ
ク図、第５図は第４図の回路のスイミング・チヤ
ート、および第６図は第４図の回路の位相差の周
波数特性曲線図である。
１……ＤＡコンバータ、２，３……デイグリチ
ヤ回路（サンプル・ホールド回路）、４……ロー
パス・フイルタ、５……コントローラ、６……デ
イジタル信号処理回路。
Fig. 1 is a block diagram of a DA conversion circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram of a digital signal processing circuit 6, Fig. 3 is a frequency characteristic curve of phase difference, and Fig. 4 is a diagram of a conventional example. FIG. 5 is a swimming chart of the circuit of FIG. 4, and FIG. 6 is a frequency characteristic curve diagram of the phase difference of the circuit of FIG. 4. DESCRIPTION OF SYMBOLS 1...DA converter, 2, 3... Degrichier circuit (sample/hold circuit), 4... Low pass filter, 5... Controller, 6... Digital signal processing circuit.
Claims (1)
ジタル信号をアナログ信号に変換するデイジタル
−アナログ変換器と、その出力を複数チヤンネル
のアナログ信号にするために相補動作する複数の
デイグリチヤ回路またはサンプル・ホールド回路
とを有するデイジタル・アナログ変換回路におい
て、前記複数チヤンネルのアナログ信号間の位相
差を補償するデイジタル信号処理回路を、前記デ
イジタル−アナログ変換器の前段に設けたことを
特徴とするデイジタル−アナログ変換回路。 A digital-to-analog converter that converts digital signals of multiple channels that are input in a sequential time-sharing manner into analog signals, and a plurality of deglitch circuits or sample-and-hold circuits that operate complementary to each other to convert the outputs to analog signals of multiple channels. 1. A digital-to-analog conversion circuit comprising: a digital signal processing circuit for compensating the phase difference between the analog signals of the plurality of channels, provided at a stage upstream of the digital-to-analog converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18295485U JPS6293835U (en) | 1985-11-29 | 1985-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18295485U JPS6293835U (en) | 1985-11-29 | 1985-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6293835U true JPS6293835U (en) | 1987-06-15 |
Family
ID=31129235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18295485U Pending JPS6293835U (en) | 1985-11-29 | 1985-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6293835U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0199323A (en) * | 1987-10-12 | 1989-04-18 | Nippon Columbia Co Ltd | Digital analog converter circuit |
-
1985
- 1985-11-29 JP JP18295485U patent/JPS6293835U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0199323A (en) * | 1987-10-12 | 1989-04-18 | Nippon Columbia Co Ltd | Digital analog converter circuit |