JPH0199323A - Digital analog converter circuit - Google Patents

Abstract

PURPOSE:To process two digital signals by one D/A converter by converting a parallel digital data into a serial digital data while time delay is corrected, converting it into a serial analog data and obtaining a parallel analog data from the serial analog data. CONSTITUTION:Digital signals L(D), R(D) are subject to oversampling by digital filters 1, 2. As a result, data 12A1, 12B1, 12A2, 12B2,...12Bn subject to double oversampling are obtained. The parallel data (c, d) having a double sampling frequency are converted into a serial data by a parallel serial converter 3. Thus, the analog data without time delay is obtained by one D/A converter.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a D/A conversion circuit that converts a multi-channel digital signal such as a stereo signal into an analog signal.

(Prior Art) In digital equipment such as compact disc (AN) players, digital data of multiple channels such as stereo left and right signals are arranged in series, and this is
When converting, it is necessary to correctly match the phase between each channel.

For this purpose, in the past, each channel data was converted into parallel data, and independent D/A converters were used to drive them with the same clock to perform D/A conversion. However, this is expensive and requires the use of multiple A/A converters.

Also, in the case where one ODA converter is used to D/A convert the serial data of the stereo left and right signals in the same order, and the sample and hold circuit extracts each of the stereo left and right signals to obtain an analog stereo signal. is subjected to serial KD/A conversion, so one channel is temporally delayed by a half cycle of the sampling period.

For this reason, another stage of sample-and-hold circuit is added to the more advanced channel, and the phase is adjusted by delaying the signal by half a cycle.

(Problem to be Solved by the Invention) However, although this type of A/A conversion circuit eliminates the phase shift, one channel has an additional sample and hold circuit, which causes an increase in distortion and noise. However, it was easy to get unbalanced characteristics between channels. 1 In view of these points, the present invention provides a digital-to-analog conversion circuit that can process two digital signals with one D/A converter and has less deterioration of characteristics. For this reason, in the present invention, when converting parallel digital data of multiple channels into one serial digital data, the data of each channel is corrected according to the time at which the data should be arranged. Then, serial digital data is obtained based on this corrected digital data, this is added to one D/A converter to obtain a series analog data string, and this is further applied to multiple sampling circuits corresponding to the above-mentioned multiple channels. In addition, each analog data for the plurality of channels is reproduced by sequential sampling.

(Operation) As mentioned above, since the serial data arranged in sequence is assigned by estimating the true data at that time, it is converted into serial analog data by one D/A converter. By converting the signal into a column and sampling and holding it at the phase of each channel, the analog data of each channel can be demodulated.

(Embodiment) FIG. 1 shows an embodiment in which the present invention is applied to a digital analog conversion circuit that obtains an analog signal from stereo left and right parallel digital signals.

In the figure, stereo left and right digital signals L(D)
, R(D) are applied to double oversampling digital filters 1 and 2, and their outputs are applied to a D/A converter 4 via a parallel-to-serial converter 3. D/
The output of the A converter 4 is applied to sample and hold circuits 5 and 6, sampled and held by the sample and hold signal f9g from the sampling signal generator 7, and converted into left and right analog signals L (A) and R (A). converted.

The operation of the above configuration will be explained using the waveform diagram of each part in FIG. FIG. 2 shows the case where the input digital signals L(D) and R(D) in FIG. The output waveform indicated by -k is shown.゛
1 waveforms a and b are data values 1 at each sampling time of parallel digital data L (D) and R (D) obtained by sampling the stereo left and right signal flow portions 10 at the basic sampling period T.] I.

112,...11. This shows that. These digital signals L(D) and R(D) are oversampled twice by digital filters 1 and 2. As a result, the intermediate data of each basic sampling period is interpolated as shown in FIG. , 12A,
, 12B2 , . . . 12B are obtained. Parallel data (c
, d) are converted into serial data by the parallel-to-serial converter 3. In this case, in the first half of the basic sampling synchronization T, the data 12A, 12A2, 12A, of the output C from the left channel digital filter 1.

...12A, is extracted and assigned, and in the second half, data 12B, 12B2.12B, ...12B of the output d from the right channel digital filter 2.

Extract and assign. That is, for the left channel, the input digital data L(D) is used as is, and for the right channel, the intermediate data of the sampling interval generated by the digital filter 15EI) is used to convert these left and right data into serial data.

In this way, the subscripts in Figure 2 e are serial data 12A□, 12B, l, 12A2, where the sampling phase differs by 180 degrees in the left and right channels, as usual.
・12 A and R are obtained. This serial data is D/
After being subjected to fi D/A conversion by the A conversion circuit 4, left and right channel analog data are output alternately, making it possible to obtain serial analog data. This analog data is sampled and held by sampling and holding circuits 5 and 6. Left in this case.

The sample hold pulse f+g for the right channel is composed of pulses 13 and 14 having a phase difference of 180'' from each other as shown in the figure, and is output from the left and right serial analog data of the D/A converter circuit 4 to the analog output L for the left channel, respectively. (
A) and right channel analog output L (B) are extracted as shown in the waveform and k.

In the above example, the left side is used to align the delay times.

Both right channels were processed by a digital filter, but only the right channel was processed by a digital filter to obtain data 12 at the middle of the sampling interval shown in Fig. 2d.
B,,12B,'...12B5 is generated, and this generated data is used as data for the right channel, and for the left channel, a delay is given to compensate for the delay of the digital filter for the right channel, and the data for the left channel is It is of course possible to obtain serial data as shown in FIG. 2e by serially converting these left and right channel data.

Further, the present invention is not necessarily limited to a two-channel signal such as the stereo signal described above, and can be applied to a signal having any number of channels. For example, in the case of four channels, the input digital signal may be sampled and calculated and converted into serial data.

Furthermore, as described above, the means for generating intermediate data at sampling times is not necessarily limited to oversampling digital filters; for example, in the case of two-channel data, digital data at sampling times before and after that can be used as intermediate data. You may calculate the average value of and use it.

- (Effects) As described above, according to the present invention, parallel digital data can be
Convert to serial digital data with time delay corrected, convert it to serial analog data using one D/A converter circuit, sample and hold analog data for left and right channels from this serial analog data, and convert to parallel analog data. Therefore, the D/A converter is 1
Analog data without time delay can be obtained by simply using one.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of each part to explain its operation. 1.2...Digital filter 3...Parallel/serial conversion circuit 4...D/A converter 5.6...Sampling hold circuit 7...Sampling signal generator IEI

Claims (1)

[Claims] a plurality of channels of parallel digital data receiving means; a correction means for correcting the parallel digital data for a delay according to a data arrangement in the serial digital data corresponding to the parallel digital data; a D/A converter for converting the serial digital data into serial analog data; and a sampling means for extracting analog data corresponding to each channel from the serial analog data. A digital-to-analog conversion circuit.