JPS60232731A - Method for converting sampling frequency of digital signal - Google Patents

Abstract

PURPOSE:To obtain an output of high quality with a simple constitution also in a case other than the conversion of an integer ratio by making the 1st digital value approximate to the 2nd digital value linearly and individually adding a random number to the linearly approximated digital value to sample the digital value on the basis of the added value. CONSTITUTION:An input digital signal Di from a terminal F1 is processed by a delay circuit 1, a subtracter 2, a divider 3, and the 1st holding circuit 4 on the basis of a clock signal from a terminal F2 and the output of the circuit 4 is applied to the 1st adder 5. The output of the adder 5 is applied to the 2nd holding circuit 7 through a multiplexer M and the output of the circuit 7 is applied to the adder 5. The multiplexer M and the circuit 7 are controlled by a clock from a clock generator 6, the 1st and 2nd digital values are linearly approximate and the approximated digital value is supplied to the 2nd adder 8. The adder 8 adds a random number from a random number generator 9 to the linearly approximated digital value and the digital value is sampled on the basis of the added value. Thus, the quality of the output can be improved also in a case other than the conversion of an integer ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a sampling frequency conversion method for digital signals obtained by sampling analog signals.

BACKGROUND TECHNOLOGY In the prior art, when converting a sampling frequency, a digital/analog converter converts a digital signal back into an analog signal, and then the converted analog signal is sampled at a sampling frequency. A common method is to convert the signal back into a digital signal using a converter.

In this method, once a digital signal is converted into an analog signal, electrical noise is mixed into the analog signal, resulting in a poor output signal/noise ratio.

Also, digital/analog and analog/digital
Converting degrees causes distortion in the signal.

When sampling frequency conversion is performed using an integer ratio, a deinotal filter is used, but the processing circuit becomes complicated and large-scale. This method also has the disadvantage that the conversion ratio must be an integer.

Purpose An object of the present invention is to solve the above-mentioned technical problems and provide a digital signal sampling frequency conversion method that has a simple configuration, does not require integer ratio conversion, and can obtain high-quality output. It is to be.

Embodiment FIG. 1 is a block diagram of a digital signal sampling frequency conversion system according to an embodiment of the present invention. An input digital signal Di obtained by sampling an analog signal at a certain sampling frequency is applied to a terminal F1. Input clock signal C
i is applied to the terminal F2 in synchronization with the sampling frequency of the input digital signal Dif') and the rising edge of the input digital signal Dif'. The delay circuit 1 receives the input digital signal Di and the input clock signal c1, delays the input digital signal D1 by the period T1 of the input clock signal C1, and then outputs the subtraction circuit 2.
is output to multiplexer M. The subtraction circuit 2 has a terminal F
The output value of the delay circuit 1 is subtracted from the input digital signal Di given to the input digital signal Di, and the result is output to the division circuit 3. The division circuit 3 divides the output value of the subtraction circuit by a predetermined value N. The third holding circuit 4 inputs the input clock signal Ci and holds the output from the division circuit 3 for a period T1 of the input clock signal Ci.
Output to.

The clock generation circuit 6 inputs the input clock signal C1, generates a clock signal Cc having a frequency that is a multiple of the predetermined value N, and generates a line! 1 to the second holding circuit 7. Furthermore, the clock generation circuit 6 generates
A pulse having a pulse width of one period T2 of the clock signal Cc is line! 2 to the multiplexer M.

The multiplexer M provides the output from the delay circuit 1 to the second holding circuit 7 in synchronization with the fall of the clock signal Cc from the clock generation circuit 6, and provides the output from the adder circuit 5 in synchronization with the rise of the clock signal Cc. The second holding circuit 7
I will appear on. The second holding circuit 7 holds and outputs the output from the delay circuit 1 for a period T2 of the clock signal Ci in synchronization with the rise of the clock signal Cc. Further, the second holding circuit 7 holds and outputs the output from the first addition circuit 5 for the one period T20 in synchronization with the fall of the clock signal Cc. The second holding circuit 7 outputs to the second addition circuit 8 and also feeds back the output to the first addition circuit 5. The adder circuit 5 adds the output from the first holding circuit 4 and the output from the second adder circuit 8 and outputs the result to the multiplexer M.

The $2 addition circuit 8 adds the output value of the second holding circuit 7 and the output value a of the random number generated by the random number generator 9,
It is output to the third holding circuit 10.

The random number has positive and negative values. Third holding circuit 10
holds the output from the second adder circuit 8 for one cycle of the output clock signal Co applied to the terminal F3 and outputs it to the terminal F4. The frequency of this output clock signal Co becomes the sampling frequency of the converted output digital signal Do.

The operation according to this method will be described below with reference to timing chart 1 in FIG. An input digital signal Di having a sampling frequency period T1 as shown in FIG. 2(3) is applied to the terminal F1.

Moreover, the period T1 as shown in FIG. 2 (2) is connected to the terminal F2.
An input clock signal C1 is provided.

The input digital signal D1 is applied to the terminal F1 in synchronization with the rising edge of the input clock signal Ci. Terminal F1
An input digital signal Di(n
) value is input to a delay circuit 1 and a subtraction circuit 2. Here, the reference mark (n) indicates one period, and the same applies in the following description.

In the subtraction circuit 2, the input digital signal Di(n) value is the input digital signal Di one period before the input digital signal Di(n) value, which is delayed by the delay circuit 1 as shown in FIG. 2(4). (n-1) values are subtracted. The output of the subtraction circuit 2 is divided by a predetermined value N in a division circuit 3. This calculation is expressed by the first equation (1). The first holding circuit 4 has an input clock signal C.
When i falls, the output ΔDn-1 value of the divider circuit 3 is held for a period T1, and an output as shown in FIG. 2 (6) is given to the adder circuit 4.

On the other hand, the multiplexer M inputs a pulse as shown in FIG. The digital signal Di(n-1) value is output to the second holding circuit 7. The second holding circuit 7 holds the digital signal Di(n-1) in synchronization with the rise of the clock signal Cc.

At the next rising edge of the clock signal Cc, the second
The digital signal Di(n−
1) The value and the output ΔDn-1 value of the first holding circuit 3 are added by the adding circuit 5 and inputted to the second holding circuit 7 again. Thereafter, at the rising edge of the clock signal C'c, the output of the second holding circuit 7 becomes as shown in Table 1 with reference to FIG. 2 (7).

(Left below) tIS1 table Di(n-1) b Di(n-1)+ 2 XΔDn-1c Di
(n-1)+3XΔDn-1 d Di(n-1)+4 XΔDn-1n Di
The (n-1)+(N-1)XΔDn-1 multiplexer M transfers the next digital signal Di(n) from the delay circuit 1 to the second holding circuit in synchronization with the falling edge of the next input clock signal C1. Give to 7.

By performing the above-mentioned operations, the difference between the discretely inputted input digital signal Di(n-1) value and the adjacent input digital signal Di(n) value is converted into a digital signal in a stepwise manner. The value can be approximated by a straight line.

A second addition circuit 8 adds a random number value a from a random number generator 9 to this stepped linear approximation digital signal value. This reduces the distortion of the signal that occurs in the part where the linearly approximated digital signal value changes in a stepwise manner.

The output of the second adder circuit 8 obtained in this way is the third
It is input to the holding circuit 10. The third holding circuit 10 receives an output clock signal Co as shown in FIG. 2 (8) from a terminal F, and the output of the second addition circuit 8 is held for a period T3 of the output clock signal Co. Ru. The output of this third holding circuit is as shown in Fig. 2 (9), and the output D for one period is
o(m) is expressed by the following second equation.

D o (m) = D i (n −1) tennXΔDn −
1+ (r-(2) In the second equation, n is the output clock signal C.

The output value of the second holding circuit 7 at the time of rising of is shown. The frequency of the output clock signal Co becomes the sampling frequency of the converted output digital signal Do. Third holding circuit 1
The output digital signal Do from zero is applied to the terminal F4. Note that in FIG. 2, the timing of each signal is shown with a predetermined value N being 8.

FIG. 3 shows the state of a digital signal subjected to linear approximation. FIG. 3 is similar to the structure of FIG. 2, and corresponding parts are given the same reference numerals. The output from the second holding circuit 7 is shown by a broken line 40, and the output from the second addition circuit 8 is shown by a solid line 50.
It is shown in In this way, the digital signal is brought closer to the original analog signal.

In the above system, in order to obtain a high-quality output, it is desirable that the frequency of the output clock signal Co, which is the sampling frequency after conversion, be lower than that of the clock signal Cc.

Effects As described above, according to the present invention, the conversion ratio of the sampling frequency does not need to be an integer ratio, and high-quality output can be obtained with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing chart for explaining the method shown in the figure. FIG. 3 is a diagram showing the state of a digital signal subjected to linear approximation. 2...Subtraction circuit, 3...Division circuit, 5...First addition circuit, 8...Second addition circuit, 9...Random number generator agent Patent attorney Kei Nishi

Claims (1)

[Claims] A method of sampling an analog signal at a first Umemoto frequency and converting the sampled pulse from the @1 Umemoto frequency of the sampled digital signal to a second sampling frequency according to the amplitude, The difference between the adjacent first digital value and second digital value sampled at the first sampling frequency is calculated, the first digital value and the second digital value are approximated by a straight line, and the linearly approximated digital value is calculated. A sampling frequency conversion method for digital signals in which random numbers are individually added to the values, and then the digital values to which the random numbers have been added are sampled at a second sampling frequency.