JPS6048945B2 - special effects waveform generator - Google Patents

special effects waveform generator

Info

Publication number
JPS6048945B2
JPS6048945B2 JP6232477A JP6232477A JPS6048945B2 JP S6048945 B2 JPS6048945 B2 JP S6048945B2 JP 6232477 A JP6232477 A JP 6232477A JP 6232477 A JP6232477 A JP 6232477A JP S6048945 B2 JPS6048945 B2 JP S6048945B2
Authority
JP
Japan
Prior art keywords
waveform
circuit
converter
output
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6232477A
Other languages
Japanese (ja)
Other versions
JPS53147431A (en
Inventor
英雄 秋山
憲彦 井手下
賢二 橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP6232477A priority Critical patent/JPS6048945B2/en
Publication of JPS53147431A publication Critical patent/JPS53147431A/en
Publication of JPS6048945B2 publication Critical patent/JPS6048945B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 本発明はテレビジョン特殊効果に使用する特殊効果波形
発生器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a special effects waveform generator for use in television special effects.

従来、特殊効果波形発生器の基本波となる、鋸歯状波、
三角波及びパラボラ波等を得るために、デジタル演算に
よつてこれらのデジタル信号発生させ、このデジタル信
号からデジタルアナログ(D/A)変換器によつて、ア
ナログ信号に変換された基本波を作る場合があつた。
Traditionally, the sawtooth wave, which is the fundamental wave of special effects waveform generators,
In order to obtain triangular waves, parabolic waves, etc., these digital signals are generated by digital calculation, and a fundamental wave is created from this digital signal by converting it into an analog signal using a digital-to-analog (D/A) converter. It was hot.

この場合デジタルアナログ変換器出力の階段状に変化す
る信号をローパスフィルタに通して滑らかな基本波を得
ていた。しかしこのローパスフィルタではパルス応答特
性の有好なものは多数の素子を必要とし比較的複雑なも
のであつた。
In this case, the stepwise changing signal output from the digital-to-analog converter was passed through a low-pass filter to obtain a smooth fundamental wave. However, this low-pass filter requires a large number of elements and is relatively complex in order to have good pulse response characteristics.

またデジタル演算回路の演算速度を早くすれは有利てあ
るが、早くすることは使用するデジタル演算素子、D/
A変換器等の消費電力増加などの点で不利なものがあつ
た。フ したがつて本発明の目的は高性能のローパスフ
ィルタを用いることなく、滑らかな基本波を得ることが
できる特殊効果波形発生器を提供することである。本発
明による特殊効果波形発生器によれば、5D/A変換器
の後段に変換出力の階段状の変化を細かくする波形成形
回路を具備した特殊効果波形発生器が得られる。次に本
発明の一実施例を示した図面を参照して本発明を詳細に
説明する。
Also, it is advantageous to increase the calculation speed of the digital calculation circuit, but increasing the calculation speed of the digital calculation element used, D/
There were disadvantages in terms of increased power consumption of the A converter, etc. Therefore, an object of the present invention is to provide a special effect waveform generator that can obtain a smooth fundamental wave without using a high-performance low-pass filter. According to the special effect waveform generator according to the present invention, a special effect waveform generator can be obtained which is provided with a waveform shaping circuit that makes fine step-like changes in the converted output after the 5D/A converter. Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

第1図は本発明の一実施例の構成図であり、データセレ
クタ1で水平及び垂直の特殊効果基本波 ;の傾きがそ
れぞれ設定される。
FIG. 1 is a block diagram of an embodiment of the present invention, in which a data selector 1 sets the slopes of horizontal and vertical special effect fundamental waves, respectively.

設定されたデータは水平デジタル演算回路2及び垂直デ
ジタル演算回路3て順次加算される。水平高調波信号発
生回路4ては、端子5から供給されてくる水平同期信号
が逓倍(例えば7倍)され、水平デジタル演算回路2に
おける演算のタイミングをとるクロック信号となる。垂
直デジタル演算回路3の演算タイミングは水平同期信号
のタイミングで行なわれる。
The set data is sequentially added by the horizontal digital arithmetic circuit 2 and the vertical digital arithmetic circuit 3. In the horizontal harmonic signal generation circuit 4, the horizontal synchronization signal supplied from the terminal 5 is multiplied (for example, by a factor of 7), and becomes a clock signal for timing calculations in the horizontal digital calculation circuit 2. The calculation timing of the vertical digital calculation circuit 3 is performed at the timing of the horizontal synchronization signal.

D/A変換器6,7はそれぞれ水平デジタル演算回路2
と垂直デジタル演算回路3との出力をアナログ信号に変
換するものである。波形成形回路8,9はD/A変換器
の出力の階段状の変化を細かくするものであり、説明は
後にする。
D/A converters 6 and 7 are each horizontal digital arithmetic circuit 2
and the vertical digital arithmetic circuit 3 are converted into analog signals. The waveform shaping circuits 8 and 9 are for making the step-like changes in the output of the D/A converter finer, and will be explained later.

波形成形回路8,9の出力は混合回路10で混合される
。混合出力は比較回路11で端子12からのフエーダー
制御電圧と比較され画面を切替える特殊効果波形が得ら
れる。波形成形回路8,9以外は特願昭52−3254
2号(特開昭53−117325号)明細書に詳細に説
明して−あるので説明は省く。
The outputs of the waveform shaping circuits 8 and 9 are mixed in a mixing circuit 10. The mixed output is compared with the fader control voltage from the terminal 12 in a comparator circuit 11 to obtain a special effect waveform for switching the screen. Other than waveform shaping circuits 8 and 9, patent application No. 52-3254
No. 2 (Japanese Unexamined Patent Publication No. 117325/1989) describes this in detail, so the explanation will be omitted.

次に波形成形回路8,9について構成、動作を説明する
Next, the configuration and operation of the waveform shaping circuits 8 and 9 will be explained.

第2図は波形成形回路の一例を示す図であり、第3図は
動作を説明するための波形図てある。D/A変換器から
の出力波形S,が波形成形回路の入力端子13に供給さ
れる。
FIG. 2 is a diagram showing an example of a waveform shaping circuit, and FIG. 3 is a waveform diagram for explaining the operation. An output waveform S from the D/A converter is supplied to an input terminal 13 of the waveform shaping circuit.

波形S,は周期T,ごとにアナログ量Aだけ変化する図
示されたような波形とする。波形S,は援衝増幅器14
を経て、抵抗15と遅3延線16との直列回路と、前記
直列回路と並列になつている抵抗17とに加えられる。
The waveform S is assumed to be a waveform as shown, which changes by an analog amount A every period T. The waveform S, is the impulse amplifier 14
The signal is then applied to a series circuit of a resistor 15 and a delay line 16, and a resistor 17 connected in parallel with the series circuit.

遅延線16の遅延量はT,/2であり、抵抗値は遅延線
16の特性インピーダンスと等しくされる。このとき援
衝増幅器18の入力側には、まずA/2の振幅4・の電
圧が発生し時間T,/2後になつてAの振幅となつてゆ
く波形S。が現われる。このため援衝増幅器18の入力
インピーダンスは十分に高いものを使用している。援衝
増幅器18の出力を更に抵抗19と遅延線,20の直列
回路と、前記直列回路と並列になつている抵抗21とに
加えられると援衝増幅器22の出力には波形S3のよう
な信号が得られる。
The delay amount of the delay line 16 is T,/2, and the resistance value is made equal to the characteristic impedance of the delay line 16. At this time, on the input side of the impulse amplifier 18, a voltage with an amplitude of A/2 of 4.times. is first generated, and after a time T,/2, a waveform S becomes the amplitude of A. appears. For this reason, the input impedance of the impulse amplifier 18 is set to be sufficiently high. When the output of the boosting amplifier 18 is further applied to a series circuit of a resistor 19, a delay line, and 20, and a resistor 21 connected in parallel with the series circuit, the output of the boosting amplifier 22 produces a signal having a waveform S3. is obtained.

このとき遅延線20の遅延量はT1/4に選ばれ、抵抗
値は遅延線20の特性インピーダンスと等しく選クばれ
る。援衝増幅器14,18,22はいずれも高い入力イ
ンピーダンスと低い出力インピーダンスをもつものが使
用される。
At this time, the delay amount of the delay line 20 is selected to be T1/4, and the resistance value is selected to be equal to the characteristic impedance of the delay line 20. The boosting amplifiers 14, 18, and 22 are all used with high input impedance and low output impedance.

したがつて波形成形回路の出力には、D/A変7換器の
階段状の出力信号が更に細分化したアナログ信号が得ら
れる。
Therefore, an analog signal obtained by further subdividing the stepped output signal of the D/A converter 7 is obtained as the output of the waveform shaping circuit.

この様に入力の階段状信号を細分化する波形成形回路と
比較的高い周波数成分を除去するローパスフィルタとを
組み合せて、デジタル演算速度を上げることなく滑らか
な波形をJ得ることができる。例えば、水平高調波信号
発生回路で、水平同期信号を256(?)倍した信号を
作り、この信号によつて水平デジタル演算回路2の演算
を行なつた場合、波形成形回路8における遅延線の遅延
量は1段目が124ns)2段目が62ns)更に3段
となつた場合3段目は31nsとなる。
In this way, by combining the waveform shaping circuit that subdivides the input stepwise signal and the low-pass filter that removes relatively high frequency components, a smooth waveform can be obtained without increasing the digital calculation speed. For example, if a horizontal harmonic signal generation circuit generates a signal that is 256 (?) times the horizontal synchronization signal, and this signal is used to perform calculations in the horizontal digital calculation circuit 2, the delay line in the waveform shaping circuit 8 The delay amount is 124 ns for the first stage, 62 ns for the second stage, and 31 ns for the third stage when there are three stages.

この場合なめらかなアナログ信号を得ることができる。
なお垂直デジタル演算回路3より後段も同様に行える。
波形成形回路8および9の一方、特に垂直波形回路9を
省略することも可能である。
In this case, a smooth analog signal can be obtained.
Note that the same process can be performed in the stages subsequent to the vertical digital arithmetic circuit 3.
It is also possible to omit one of the waveform shaping circuits 8 and 9, especially the vertical waveforming circuit 9.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示した図、第2図は波形成
形回路の構成図、第3図は波形成形回路の動作を説明す
るための波形図、図において、1 ・・・デジタルデー
タセレクタ、2・・・水平デジタル演算回路、3・・・
垂直デジタル演算回路、4 ・・・水平高調波信号発生
回路、6,7・・・D/A変換回路、8,9・・・波形
成形回路、10・・・混合回路、11・・・比較回路、
14,18,22・・・・・・援衝増幅器、16,20
・・・遅延線。
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a waveform shaping circuit, and FIG. 3 is a waveform diagram for explaining the operation of the waveform shaping circuit. Digital data selector, 2... horizontal digital arithmetic circuit, 3...
Vertical digital arithmetic circuit, 4...Horizontal harmonic signal generation circuit, 6, 7...D/A conversion circuit, 8, 9...Waveform shaping circuit, 10...Mixing circuit, 11...Comparison circuit,
14, 18, 22... Encouragement amplifier, 16, 20
...delay line.

Claims (1)

【特許請求の範囲】[Claims] 1 第一及び第二のデータを設定できて前記第一及び第
二のデータに対応した第一及び第二のデジタルデータを
それぞれ出力するデータセレクタと、前記第一のデータ
を水平同期信号を逓倍した信号のタイミングで順次加算
あるいは減算する第一のディジタル演算回路と、前記第
二のデータを垂直同期信号を逓倍した信号あるいは水平
同期信号のタイミングで順次加算あるいは減算する第二
のディジタル演算回路と、前記第一のディジタル演算回
路の出力をアナログ信号に変換する第一のディジタルア
ナログ(D/A)変換器と、前記第二のデジタル演算回
路の出力をアナログ信号に変換する第二のD/A変換器
と、前記第一および第二のD/A変換器の出力を混合す
る混合回路と、前記混合回路の出力レベルをフエーダー
制御信号のレベルと比較する比較回路とを具備した特殊
効果波形発生器において、前記第一および第二のD/A
変換器と前記混合回路との間の少なくとも一方に前記D
/A変換器の出力の階段状波形の階段を細分化する波形
成形回路を設け、前記波形成形回路が前記D/A変換器
の出力の階段状波形に対して階段周期の1/2の遅延時
間をもつ遅延波形を作る手段と、前記D/A変換器の出
力の階段状波形と前記遅延波形とを加算する手段とを含
むことを特徴とする特殊効果波形発生器。
1 A data selector that can set first and second data and outputs first and second digital data corresponding to the first and second data, respectively, and a horizontal synchronization signal that multiplies the first data. a first digital arithmetic circuit that sequentially adds or subtracts the second data at the timing of a signal obtained by multiplying the vertical synchronization signal or a second digital arithmetic circuit that sequentially adds or subtracts the second data at the timing of a signal obtained by multiplying the vertical synchronization signal or a horizontal synchronization signal; , a first digital-to-analog (D/A) converter that converts the output of the first digital arithmetic circuit into an analog signal, and a second D/A converter that converts the output of the second digital arithmetic circuit into an analog signal. A special effect waveform comprising an A converter, a mixing circuit that mixes the outputs of the first and second D/A converters, and a comparison circuit that compares the output level of the mixing circuit with the level of a fader control signal. In the generator, the first and second D/A
the D at least on one side between the converter and the mixing circuit;
A waveform shaping circuit is provided to subdivide the staircase of the staircase waveform of the output of the D/A converter, and the waveform shaping circuit has a delay of 1/2 of the staircase period with respect to the staircase waveform of the output of the D/A converter. A special effect waveform generator comprising: means for creating a delayed waveform having time; and means for adding the stepped waveform output from the D/A converter and the delayed waveform.
JP6232477A 1977-05-27 1977-05-27 special effects waveform generator Expired JPS6048945B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6232477A JPS6048945B2 (en) 1977-05-27 1977-05-27 special effects waveform generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6232477A JPS6048945B2 (en) 1977-05-27 1977-05-27 special effects waveform generator

Publications (2)

Publication Number Publication Date
JPS53147431A JPS53147431A (en) 1978-12-22
JPS6048945B2 true JPS6048945B2 (en) 1985-10-30

Family

ID=13196836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6232477A Expired JPS6048945B2 (en) 1977-05-27 1977-05-27 special effects waveform generator

Country Status (1)

Country Link
JP (1) JPS6048945B2 (en)

Also Published As

Publication number Publication date
JPS53147431A (en) 1978-12-22

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