JPH02130019A - Voltage controlled delay circuit - Google Patents

Abstract

PURPOSE:To facilitate the miniaturization and the integration of a circuit by providing a multiplication circuit and a frequency division circuit to n-frequency divide the output of a voltage comparison circuit comparing the output signal of a saw tooth wave generation circuit with control voltage. CONSTITUTION:Clock input A is converted into a multiplied clock B by an n-multiplication circuit 1, and becomes the trigger input of the saw tooth wave generation circuit 2. The output C of the saw tooth wave generation circuit 2 and control voltage input D are inputted to a comparator 3, and converted into a delayed n-times clock E whose rise or fall is delayed behind the multiplied clock B, and further, it is converted into delayed clock output F by an n- frequency division circuit 4, and outputted. Accordingly, delay quantity 5 between the clock input A and the delayed clock output F can be obtained, and the control voltage D is changed. Thus, the control voltage can be changed continuously, and the integration can be facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit for a clock signal in a digital circuit, and more particularly to a voltage-controlled delay circuit whose delay amount can be controlled by voltage.

[Conventional technology]

Conventionally, this type of delay circuit has been constructed using a tapped delay line 6 configured with multiple passive circuits as shown in FIG. 3, and a gate section consisting of an input buffer 7 and an output buffer 8 for waveform shaping. There were multiple configurations, and the tap position was changed in order to obtain the desired amount of delay.

[The problem that the invention attempts to solve]

In the method using the conventional passive delay line 7 described above, the accuracy and variable range of the delay amount are limited by the number of taps, so a large number of taps must be provided in order to perform fine delay control. won. Further, since the passive delay line 7 itself is composed of parts such as coil capacitors, there is a problem that miniaturization and integration are difficult.

[Means to solve the problem]

The voltage controlled delay circuit of the present invention has an input clock signal of n
A multiplier circuit that performs multiplication (n: a positive integer), a sawtooth wave generation circuit that uses the output signal of the multiplier circuit as a trigger, and a voltage comparison circuit that compares the output signal of the sawtooth wave generation circuit with a control voltage.
It is composed of a frequency dividing circuit that divides the output of the comparator circuit by n and K.

[Effect]

In the present invention, a continuous amount of delay can be obtained depending on the control voltage.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a voltage controlled delay circuit according to the present invention. In the same figure, clock power A is n
The multiplier circuit 1 converts the signal into a multiplier clock B, which serves as a trigger input to the sawtooth wave generator circuit 2. The output C of the sawtooth wave generating circuit 2 and the control voltage input are input to the comparator circuit 3, where they are converted into a delayed single clock E in which the rising edge or falling edge is delayed with respect to the multiplied clock B, and then n The frequency dividing circuit 4 converts the signal into a delayed clock output F and outputs it.

FIG. 2 is a waveform diagram showing input and output waveforms of signals at each point in FIG. 1 when n=2. As shown in the figure, a delay amount of 5 between the clock input A and the delayed clock output F is obtained, and can be changed continuously by changing the control voltage.

[Effects of the Invention] As explained above, the voltage-controlled delay circuit according to the present invention has the extremely excellent effect of being able to obtain a continuous delay amount according to the control voltage and facilitating integration. It will be done.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a voltage-controlled delay circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms at each point in FIG. 1, and FIG. 3 is a diagram of a conventional delay circuit. . 1.ΦΦ.n multiplier circuit, 2... excellent sawtooth wave generation circuit,
3...Fist comparison circuit, 4...Fist@n frequency division circuit, 5...e
・Delay amount, 6a-...Delay line with tap, 7Φ...Input buffer, 8...Reference output buffer.

Claims (1)

[Claims] Compare a multiplier circuit that multiplies the input clock signal by n (n: a positive integer), a sawtooth wave generation circuit that uses the output signal of this multiplier circuit as a trigger input, and the output signal of this sawtooth wave generation circuit and the control voltage. 1. A voltage-controlled delay circuit comprising: a voltage comparison circuit that divides the output of the voltage comparison circuit; and a frequency division circuit that divides the output of the voltage comparison circuit by n.