JPH02130019A - Voltage controlled delay circuit - Google Patents
Voltage controlled delay circuitInfo
- Publication number
- JPH02130019A JPH02130019A JP63282321A JP28232188A JPH02130019A JP H02130019 A JPH02130019 A JP H02130019A JP 63282321 A JP63282321 A JP 63282321A JP 28232188 A JP28232188 A JP 28232188A JP H02130019 A JPH02130019 A JP H02130019A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock
- output
- control voltage
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はディジタル回路におけるクロック信号用の遅延
回路に関し、特に電圧によシ遅延量を制御可能とした電
圧制御型遅延回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit for a clock signal in a digital circuit, and more particularly to a voltage-controlled delay circuit whose delay amount can be controlled by voltage.
従来、この糧の遅延回路は、第3図に示すように受動回
路によ多構成したタップ付遅延線6と、波形整形を行な
うための入力バッファ7および出力バッファ8からなる
ゲート部とによ多構成し、所望の遅延量を得るためにタ
ップ位置を切換える構成となっていた。Conventionally, this type of delay circuit has been constructed using a tapped delay line 6 configured with multiple passive circuits as shown in FIG. 3, and a gate section consisting of an input buffer 7 and an output buffer 8 for waveform shaping. There were multiple configurations, and the tap position was changed in order to obtain the desired amount of delay.
上述した従来の受動遅延線7を用いた方法では、遅延量
の精度および可変範囲がタップ数によシ制限されるため
、細かな遅延制御を行なうためにはタップ数を数多く設
けなければなら々かった。また、受動遅延線7自体がコ
イルコンデンサ等の部品で構成されるため、小型化、集
積化が困難であるという問題があった。In the method using the conventional passive delay line 7 described above, the accuracy and variable range of the delay amount are limited by the number of taps, so a large number of taps must be provided in order to perform fine delay control. won. Further, since the passive delay line 7 itself is composed of parts such as coil capacitors, there is a problem that miniaturization and integration are difficult.
本発明の電圧制御型遅延回路は、入力クロック信号をn
逓倍(n:正整数)する逓倍回路と、逓倍回路の出力信
号をトリガとする鋸歯状波発生回路と、鋸歯状波発生回
路の出力信号と制御電圧とを比較する電圧比較回路と、
比較回路の出力をn分周する分周回路とKより構成され
る。The voltage controlled delay circuit of the present invention has an input clock signal of n
A multiplier circuit that performs multiplication (n: a positive integer), a sawtooth wave generation circuit that uses the output signal of the multiplier circuit as a trigger, and a voltage comparison circuit that compares the output signal of the sawtooth wave generation circuit with a control voltage.
It is composed of a frequency dividing circuit that divides the output of the comparator circuit by n and K.
本発明においては、制御電圧に応じた連続的な遅延量が
得られる。In the present invention, a continuous amount of delay can be obtained depending on the control voltage.
第1図は本発明による電圧制御型遅延回路の一実施例を
示す回路図である。同図において、クロック人力Aはn
逓倍回路1によシ逓倍クロックBに変換され、鋸歯状波
発生回路2のトリガ入力となる。鋸歯状波発生回路2の
出力Cと、制御電圧入力りは比較回路3に入力され、逓
倍クロックBに対して立上シまたは立下シが遅延した遅
延1倍クロックEに変換され、さらにn分周回路4によ
シ遅延クロック出力Fに変換され出力される。FIG. 1 is a circuit diagram showing an embodiment of a voltage controlled delay circuit according to the present invention. In the same figure, clock power A is n
The multiplier circuit 1 converts the signal into a multiplier clock B, which serves as a trigger input to the sawtooth wave generator circuit 2. The output C of the sawtooth wave generating circuit 2 and the control voltage input are input to the comparator circuit 3, where they are converted into a delayed single clock E in which the rising edge or falling edge is delayed with respect to the multiplied clock B, and then n The frequency dividing circuit 4 converts the signal into a delayed clock output F and outputs it.
第2図はn = 2の場合の第1図の各点における信号
の入出力波形を示す波形図である。同図に示すようにク
ロック入力Aと遅延クロック出力Fこの間の遅延量5が
得られ、制御電圧りを変化させることによシ、連続的に
変化することができる。FIG. 2 is a waveform diagram showing input and output waveforms of signals at each point in FIG. 1 when n=2. As shown in the figure, a delay amount of 5 between the clock input A and the delayed clock output F is obtained, and can be changed continuously by changing the control voltage.
〔発明の効果〕
以上説明したように本発明による電圧制御型遅延回路に
よれば制御電圧に応じた連続的な遅延量を得ることがで
き、集積化が容易となるという極めて優れた効果が得ら
れる。[Effects of the Invention] As explained above, the voltage-controlled delay circuit according to the present invention has the extremely excellent effect of being able to obtain a continuous delay amount according to the control voltage and facilitating integration. It will be done.
第1図は本発明の一実施例による電圧制御型遅延回路を
示す回路図、第2図は第1図における各点の波形を示す
波形図、第3図は従来の遅延回路の図である。
1・ΦΦ・n逓倍回路、2・・・優鋸歯状波発生回路、
3・・・拳比較回路、4・・拳@n分周回路、5・・e
・遅延量、6a−・・タップ付遅延線、7Φ・・・入カ
パツファ、8・・・参出力バツファ。FIG. 1 is a circuit diagram showing a voltage-controlled delay circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms at each point in FIG. 1, and FIG. 3 is a diagram of a conventional delay circuit. . 1.ΦΦ.n multiplier circuit, 2... excellent sawtooth wave generation circuit,
3...Fist comparison circuit, 4...Fist@n frequency division circuit, 5...e
・Delay amount, 6a-...Delay line with tap, 7Φ...Input buffer, 8...Reference output buffer.
Claims (1)
と、この逓倍回路の出力信号をトリガ入力とする鋸歯状
波発生回路と、この鋸歯状波発生回路の出力信号と制御
電圧とを比較する電圧比較回路と、この電圧比較回路の
出力をn分周する分周回路とを備えたことを特徴とする
電圧制御型遅延回路。Compare a multiplier circuit that multiplies the input clock signal by n (n: a positive integer), a sawtooth wave generation circuit that uses the output signal of this multiplier circuit as a trigger input, and the output signal of this sawtooth wave generation circuit and the control voltage. 1. A voltage-controlled delay circuit comprising: a voltage comparison circuit that divides the output of the voltage comparison circuit; and a frequency division circuit that divides the output of the voltage comparison circuit by n.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63282321A JPH02130019A (en) | 1988-11-10 | 1988-11-10 | Voltage controlled delay circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63282321A JPH02130019A (en) | 1988-11-10 | 1988-11-10 | Voltage controlled delay circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02130019A true JPH02130019A (en) | 1990-05-18 |
Family
ID=17650889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63282321A Pending JPH02130019A (en) | 1988-11-10 | 1988-11-10 | Voltage controlled delay circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02130019A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0576149A2 (en) * | 1992-05-27 | 1993-12-29 | Sony Corporation | High-voltage generating circuit |
JP2006139519A (en) * | 2004-11-11 | 2006-06-01 | Advantest Corp | Power supply circuit and testing device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5496948A (en) * | 1978-01-18 | 1979-07-31 | Toyo Electric Mfg Co Ltd | Digital phase shifter |
-
1988
- 1988-11-10 JP JP63282321A patent/JPH02130019A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5496948A (en) * | 1978-01-18 | 1979-07-31 | Toyo Electric Mfg Co Ltd | Digital phase shifter |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0576149A2 (en) * | 1992-05-27 | 1993-12-29 | Sony Corporation | High-voltage generating circuit |
US5438245A (en) * | 1992-05-27 | 1995-08-01 | Sony Corporation | High-voltage generating circuit |
JP2006139519A (en) * | 2004-11-11 | 2006-06-01 | Advantest Corp | Power supply circuit and testing device |
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