JPS63144614A - Digital filter circuit - Google Patents

Abstract

PURPOSE:To improve the replacement unit of an analog filter by interpolating ROM output samples by a multiple of N of the sampling period T so as to multiply the frequency of harmonic components by N/T. CONSTITUTION:A ROM reference type digital filter comprising a shift register 101, a ROM 102 and a sampling clock generating circuit 103 has a pulse string of sampling interval T. A shift register 104 is a shift register for delay, the output of the register 104 and the output of the ROM 102 are subject to arithmetic operation by an adder 105 and an amplitude 1/2 circuit 108 to obtain an output 113 of a prescribed spectrum. Moreover, an output 113 subject to arithmetic operation by an adder circuit 106 and an amplitude 1/2 circuit 109, and an output 114 subject to arithmetic operation by an adder circuit 107 and an amplitude 1/2 circuit 110 are outputs of a prescribed spectrum. A sampling clock generator 103 controls a selection circuit 111 to select and synthesize the outputs of the register 104, the amplitude 1/2 circuits 108-110, the harmonic signal is increased by N times and the degree in the change of the analog filter inserted to the analog part is decreased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a table reference type digital filter,
In particular, the present invention relates to a digital filter circuit that improves the number of samplings/symbols.

[Conventional technology]

Conventionally, this type of digital filter is
C5ession C (pp, 87-90) “An
alysisand Design of a ROM
5ynthesizer as an optimu
m Digital transmit filter
Read-only memory IJROM as shown in J
The main method is to use a ROM reference type digital filter.

[Problem that the invention seeks to solve]

In the conventional method described above, harmonic components are generated at intervals of 1/T (Hz) with the data sampling rate T as a period, so the D/
An analog filter was installed after the A converter to suppress unnecessary signals.

Therefore, in a system where the data rate changes, the frequency at which harmonic components are generated also changes, requiring replacement of the analog filter. In order to reduce the frequency of analog filter replacement, it is necessary to increase the number of samplings/symbols, but this has not been possible due to the limited number of address pits in commercially available ROMs.

[Means for solving problems]

It is characterized by greatly improving the replacement unit of the analog filter by multiplying the frequency of the harmonic component by Σ.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which 1 is a data input terminal, 2 is a clock input terminal, 3 is an output terminal, 101 is a shift register, and 102 is a ROM.

103 is a sampling clock generator, and 104 is a delay shift register. Addition circuits 105 to 107 and amplitude 72 circuits 108 to 110 constitute an interpolation circuit.

111 is a selection circuit. here.

To simplify the explanation, N=4 is shown.

Shift register 01. ROM 102. RO configured by sampling clock generator 103
The M-reference type digital filter has a pulse train with a sampling interval T of 0 as shown in FIG.
(using the M expression). The output of the shift register 104 is as shown in FIG. 2(b). The output 112 calculated by the adder circuit 105 and the amplitude 72 circuit 108 is as shown in FIG. 2(C). Further, the output 113 calculated by the addition circuit 106 and the amplitude 72 circuit 109 and the output 114 calculated by the addition circuit 107 and the amplitude 72 circuit 110 are shown in FIG.
d) and (e). The sampling clock generator 103 controls the selection circuit 111 and outputs the shift register 104.

The outputs of the amplitude 72 circuits 108, 109, and 110 are selectively synthesized.

The combined result is as shown in FIG. Therefore.

The spectrum of this signal is as shown in Fig. 4 to Fig. 5, and the harmonic signal is N times higher.The degree of change in the analog filter inserted in the analog section after the single digital filter circuit is reduced, and the manufacturing process is reduced. It also has the effect of making it easier.

Figures 6 and 7 are computer simulations of the BER characteristics of this configuration (however, Figure 6 uses 16 samples,
The figure shows 32 samples), and there is almost no deterioration due to interpolation.

Note that although the example shows an interpolation circuit with N=4,
It goes without saying that the number of combined stages of the adder circuit and the 72 amplitude circuits is changed depending on K.

〔Effect of the invention〕

As described above, according to the present invention, even if the data rate changes, the degree of change in the analog filter connected after the digital filter circuit can be reduced, and manufacturing is also facilitated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing output signals of each part in FIG. 1, and FIG. 3 is a diagram showing output signals of the selection circuit 111 in FIG. 1. FIG. 4 shows the spectrum of the output of the ROM 102 of FIG. 1, and FIG. 5 shows the output spectrum of the selection circuit 111 of FIG. FIG. 6 and FIG. 7 each show simulation results regarding the BER characteristics. In the figure, 105 to 107 are adder circuits, and 108 to 110 are amplitude 72 circuits. Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 @ Figure 7

Claims (1)

[Claims] 1. In a digital filter that receives a digital signal as an input and is configured using a read-only memory, a delay circuit that delays the output of the digital filter by a sampling period T of the digital filter, and an input and output signal of the delay circuit are provided. 1. An interpolation circuit that performs interpolation at N-1 points (N is a positive integer) using the digital filter to generate sample values of a T/N sampling period.