JPS63144614A - Digital filter circuit - Google Patents
Digital filter circuitInfo
- Publication number
- JPS63144614A JPS63144614A JP29141586A JP29141586A JPS63144614A JP S63144614 A JPS63144614 A JP S63144614A JP 29141586 A JP29141586 A JP 29141586A JP 29141586 A JP29141586 A JP 29141586A JP S63144614 A JPS63144614 A JP S63144614A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- amplitude
- rom
- digital filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims abstract description 13
- 230000001934 delay Effects 0.000 claims 1
- 238000001228 spectrum Methods 0.000 abstract description 5
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005094 computer simulation Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はテーブル参照形ディジタルフィルタ、に関し、
特にサンプリング数/シンボルの向上化を図ったディジ
タルフィルタ回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a table reference type digital filter,
In particular, the present invention relates to a digital filter circuit that improves the number of samplings/symbols.
従来、この種のディジタルフィルタは、第3回lCD5
C5ession C(pp、 87〜90) 「An
alysisand Design of a ROM
5ynthesizer as an optimu
m Digital transmit filter
Jに示されている様に、読み出し専用メモIJROM
を用いる方法が主となっており、ROM参照形ディジタ
ルフィルタとも呼ばれている。Conventionally, this type of digital filter is
C5ession C (pp, 87-90) “An
alysisand Design of a ROM
5ynthesizer as an optimu
m Digital transmit filter
Read-only memory IJROM as shown in J
The main method is to use a ROM reference type digital filter.
上述した従来の方式では、データをサンプリングする速
度Tを周期として1/T(Hz)間隔に高調波成分が発
生する為、ディジタルフィルタの後段に接続されるD/
A変換器の後にアナログフィルタを設置して不要信号を
抑圧していた。In the conventional method described above, harmonic components are generated at intervals of 1/T (Hz) with the data sampling rate T as a period, so the D/
An analog filter was installed after the A converter to suppress unnecessary signals.
従って、データ速度が変わる系では高調波成分の発生す
る周波数も変わシ、アナログフィルタの交換が必要であ
る。アナログフィルタの交換頻度を減らす為にはサンプ
リング数/シンボルを上げる必要があるが、市販されて
いるROMのアドレスピット数には限界があり実現出来
なかった。Therefore, in a system where the data rate changes, the frequency at which harmonic components are generated also changes, requiring replacement of the analog filter. In order to reduce the frequency of analog filter replacement, it is necessary to increase the number of samplings/symbols, but this has not been possible due to the limited number of address pits in commercially available ROMs.
高調波成分の周波数をΣ倍としてアナログフィルタの交
換単位を大幅に改善したことを特徴とする。It is characterized by greatly improving the replacement unit of the analog filter by multiplying the frequency of the harmonic component by Σ.
第1図は本発明の一実施例であって、1はデータ入力端
子、2はクロック入力端子、3は出力端子、101はシ
フトレジスタ、102はROM。FIG. 1 shows an embodiment of the present invention, in which 1 is a data input terminal, 2 is a clock input terminal, 3 is an output terminal, 101 is a shift register, and 102 is a ROM.
103はサンプリングクロック生成器、104は遅延用
のシフトレジスタである。加算回路105〜107、振
幅72回路108〜110は内挿回路を構成している。103 is a sampling clock generator, and 104 is a delay shift register. Addition circuits 105 to 107 and amplitude 72 circuits 108 to 110 constitute an interpolation circuit.
111は選択回路である。ここでは。111 is a selection circuit. here.
説明を簡単にする為、N=4について示している。To simplify the explanation, N=4 is shown.
シフトレジスター01. ROM 102. サン
プリングクロック生成器103によって構成されるRO
M参照形ディジタルフィルタは、第2図(a)0如<サ
ンプリング間隔Tのパルス列となっている(説明上PA
M表現を用いである)。シフトレジスタ104出力は第
2図(b)の如くなる。加算回路105と振幅72回路
108とで演算された出力112は第2図(C)の如く
なる。また、加算回路106と振幅72回路109とで
演算された出力113及び加算回路107と振幅72回
路110とで演算された出力114はそれぞれ第2図(
d) 、 (e)の如くなる。サンプリングクロック生
成器103は選択回路111を制御してシフトレジスタ
104の出力。Shift register 01. ROM 102. RO configured by sampling clock generator 103
The M-reference type digital filter has a pulse train with a sampling interval T of 0 as shown in FIG.
(using the M expression). The output of the shift register 104 is as shown in FIG. 2(b). The output 112 calculated by the adder circuit 105 and the amplitude 72 circuit 108 is as shown in FIG. 2(C). Further, the output 113 calculated by the addition circuit 106 and the amplitude 72 circuit 109 and the output 114 calculated by the addition circuit 107 and the amplitude 72 circuit 110 are shown in FIG.
d) and (e). The sampling clock generator 103 controls the selection circuit 111 and outputs the shift register 104.
振幅72回路108.109.110の出力を選択合成
する。The outputs of the amplitude 72 circuits 108, 109, and 110 are selectively synthesized.
合成された結果は第3図の如くなる。従って。The combined result is as shown in FIG. Therefore.
本信号のスペクトラムは、第4図から第5図の如くなっ
て高調波信号がN倍高に移シ1本ディジタルフィルタ回
路の後段のアナログ部に挿入するアナログフィルタの変
更度合が減り、かつ製作も容易となる効果がある。The spectrum of this signal is as shown in Fig. 4 to Fig. 5, and the harmonic signal is N times higher.The degree of change in the analog filter inserted in the analog section after the single digital filter circuit is reduced, and the manufacturing process is reduced. It also has the effect of making it easier.
第6図、第7図は本構成をBER特性について計算機シ
ミュレーション(但し、第6図は16サンプル化、第7
図は32サンプル化)したもので内挿てよる劣化は殆ん
ど見られない。Figures 6 and 7 are computer simulations of the BER characteristics of this configuration (however, Figure 6 uses 16 samples,
The figure shows 32 samples), and there is almost no deterioration due to interpolation.
なお、実施例ではN=4の内挿回路を示しているが、N
K応じて加算回路と振幅72回路との組合わせ段数が変
更されることは言うまでも無い。Note that although the example shows an interpolation circuit with N=4,
It goes without saying that the number of combined stages of the adder circuit and the 72 amplitude circuits is changed depending on K.
以上説明した如く本発明によれば、データ速度が変わっ
てもディジタルフィルタ回路の後段に接続されるアナロ
グフィルタの変更度合を減らすことができ、かつ製作も
容易となる。As described above, according to the present invention, even if the data rate changes, the degree of change in the analog filter connected after the digital filter circuit can be reduced, and manufacturing is also facilitated.
第1図は本発明の一実施例の構成図、第2図は第1図の
各部の出力信号を示した図、第3図は第1図の選択回路
111の出力信号を示した図。
第4図は第1図のROM 102の出力のスペクトラム
を示し、第5図は第1図の選択回路111出カスペクト
ラムを示す。第6図、第7図はそれぞれBER特性につ
いてのシミュレーション結果を示す。
図中、105〜107は加算回路、108〜110は振
幅72回路。
第2図
第3図
第4図
第5図
第6図
@7図FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing output signals of each part in FIG. 1, and FIG. 3 is a diagram showing output signals of the selection circuit 111 in FIG. 1. FIG. 4 shows the spectrum of the output of the ROM 102 of FIG. 1, and FIG. 5 shows the output spectrum of the selection circuit 111 of FIG. FIG. 6 and FIG. 7 each show simulation results regarding the BER characteristics. In the figure, 105 to 107 are adder circuits, and 108 to 110 are amplitude 72 circuits. Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 @ Figure 7
Claims (1)
いて構成するディジタルフィルタに於いて、該ディジタ
ルフィルタ出力を、該ディジタルフィルタのサンプリン
グ周期Tだけ遅延する遅延回路と、該遅延回路の入力及
び出力信号を用いてN−1点(Nは正整数)の内挿を行
ないT/Nサンプリング周期のサンプル値を生成する内
挿回路とを含む事を特徴とするディジタルフィルタ回路
。1. In a digital filter that receives a digital signal as an input and is configured using a read-only memory, a delay circuit that delays the output of the digital filter by a sampling period T of the digital filter, and an input and output signal of the delay circuit are provided. 1. An interpolation circuit that performs interpolation at N-1 points (N is a positive integer) using the digital filter to generate sample values of a T/N sampling period.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29141586A JPS63144614A (en) | 1986-12-09 | 1986-12-09 | Digital filter circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29141586A JPS63144614A (en) | 1986-12-09 | 1986-12-09 | Digital filter circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63144614A true JPS63144614A (en) | 1988-06-16 |
Family
ID=17768590
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29141586A Pending JPS63144614A (en) | 1986-12-09 | 1986-12-09 | Digital filter circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63144614A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5048937A (en) * | 1989-01-31 | 1991-09-17 | Hitachi Metals, Ltd. | Faraday rotator device and optical switch containing same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59218031A (en) * | 1983-05-26 | 1984-12-08 | Anritsu Corp | Signal processing circuit of combinational logic type |
JPS612482A (en) * | 1984-06-15 | 1986-01-08 | Mitsubishi Electric Corp | Sampling filter of sub-nyquist |
-
1986
- 1986-12-09 JP JP29141586A patent/JPS63144614A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59218031A (en) * | 1983-05-26 | 1984-12-08 | Anritsu Corp | Signal processing circuit of combinational logic type |
JPS612482A (en) * | 1984-06-15 | 1986-01-08 | Mitsubishi Electric Corp | Sampling filter of sub-nyquist |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5048937A (en) * | 1989-01-31 | 1991-09-17 | Hitachi Metals, Ltd. | Faraday rotator device and optical switch containing same |
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