JPS6434004A - Digital frequency generator - Google Patents

Abstract

PURPOSE:To generate a high frequency and to obtain delicate frequency variable width, by using an addition result held at an added phase data holding circuit in the next addition, and using an overflow result in the addition of a high-order digit block. CONSTITUTION:A digital arithmetic operation for the generation of a fequency is operated at an added phase step value holding circuit 1, a clock generator 2, digital adders 31 and 32, the added phase data holding circuits 41 and 42, and a high-order data delay circuit 8, and a digital value for the generation of the frequency is converted to an analog value at a waveform data ROM 5, a D/A converter 6, and a low-pass filter value 7, thereby, a processing to generate a Sin wave is performed. And added phase data is divided into the blocks having bits more than the address bit size of the waveform data ROM5, and data block is added starting from the one of low-order digit sequentially, and the whole or a part of the output data of the most significant digit block is used as a ROM address. In such a way, it is possible to set the high frequency and a delicate frequency without lowering addition speed even in a phase step value with long data width.