JPS60204032A - Pseudo random number generating circuit - Google Patents

Pseudo random number generating circuit

Info

Publication number
JPS60204032A
JPS60204032A JP59059749A JP5974984A JPS60204032A JP S60204032 A JPS60204032 A JP S60204032A JP 59059749 A JP59059749 A JP 59059749A JP 5974984 A JP5974984 A JP 5974984A JP S60204032 A JPS60204032 A JP S60204032A
Authority
JP
Japan
Prior art keywords
bit
random number
circuit
pseudo random
binary number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59059749A
Other languages
Japanese (ja)
Inventor
Hiroya Sano
佐野 博也
Takaharu Koga
古賀 隆治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Shingijutsu Kaihatsu Jigyodan
Original Assignee
Research Development Corp of Japan
Shingijutsu Kaihatsu Jigyodan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Research Development Corp of Japan, Shingijutsu Kaihatsu Jigyodan filed Critical Research Development Corp of Japan
Priority to JP59059749A priority Critical patent/JPS60204032A/en
Publication of JPS60204032A publication Critical patent/JPS60204032A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/582Pseudo-random number generators

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Spectrometry And Color Measurement (AREA)

Abstract

PURPOSE:To generate a pseudo random number at a high speed in simple constitution, by moving a low-order prescribed bit of a parallel binary number whose magnitude is varied sequentially, to a high-order prescribed bit position, and outputting it. CONSTITUTION:For instance, in a wavelength controlling circuit of a variable wavelength light source used for a spectro-photometer, a parallel binary signal varied sequentially by driving continuously an (n) bit counter 2 is generated by a clock oscillator 1, and the bit array is replaced and outputted in accordance with a prescribed rule by a pseudo random number generating circuit 3. Subsequently, this signal is held only for one clock period by a latching circuit 4, outputted to a D/A converting circuit 5, and supplied to the variable wavelength light source (not shown in the figure). In that case, in the circuit 3, for instance, a bit of an input binary number is divided into two, the upper and the lower parts, the upper part and the lower part are replaced, also, each bit of the lower half is inverted upside down, moreover, each bit of the upper half is inverted upside down, and the binary number of (4), (2), (3) and (4) is outputted as a pseudo random number.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、計測制御やデータ処理において使用される擬
似乱数信号の発止回路に関し、特に簡単な回路構成によ
る高速の擬似乱数発生回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pseudo-random number signal generation circuit used in measurement control and data processing, and particularly to a high-speed pseudo-random number generation circuit with a simple circuit configuration.

〔技術の背景〕[Technology background]

分光光度計を用いて行われるガス等の物質の吸収分析で
は、電気的に波長を連続変化できる光源を用いて物質の
吸収スペクトルを掃引して、これを計算機で処理して特
定の物質の成分濃度を算出することが行われる。この場
合、−回の掃引を行うには、最低、装置内の種々の物理
的制約により定まる一定の時間が必要とされるため、そ
の間に計測対象の物質に成分濃度の急激な変化が生じた
場合には、掃引の始めと終りとで実質的な整時性が保証
できなくなり、計算結果として得られる濃度値に、極め
て大きな誤差が含まれるおそれがある。第1図はそのよ
うな吸収スペクトルの1例を示したもので、aが正常な
場合、bが掃引中に急激な変化があった場合を示してい
る。図示のようにスペクトルの形が歪み、濃度値も異常
なものとなる。
In absorption analysis of substances such as gases performed using a spectrophotometer, a light source whose wavelength can be electrically changed continuously is used to sweep the absorption spectrum of the substance, and this is processed by a computer to identify the components of a specific substance. Calculating the concentration is performed. In this case, in order to perform - sweeps, at least a certain amount of time is required, which is determined by various physical constraints within the device. In this case, substantial timing cannot be guaranteed between the beginning and end of the sweep, and the concentration value obtained as a calculation result may contain an extremely large error. FIG. 1 shows an example of such an absorption spectrum, where a is normal and b shows a sudden change during the sweep. As shown in the figure, the shape of the spectrum is distorted and the density value also becomes abnormal.

このため従来は、予定したスペクトル領域内で波長の掃
引を端から端へ一方向に掃引するのではなく、ランダム
な順序で所定のスペクトル領域をうめつくすように掃引
する方法がとられている。
For this reason, in the past, instead of sweeping wavelengths in one direction from end to end within a predetermined spectral region, a method has been used in which wavelengths are swept in a random order to fill a predetermined spectral region.

この場合、順次の掃引位置は乱数を用いて決定されてい
るのが普通である。この結果、所定のスペクトル領域内
において一定の時間幅内で整時性をもった掃引を統計的
に実現することができる。
In this case, the sequential sweep positions are usually determined using random numbers. As a result, it is possible to statistically realize a sweep with good timing within a certain time width within a predetermined spectral region.

上述した例の場合、その他乱数処理を必要とする計測や
データ処理システムにおいては、通常、乱数を擬似乱数
によって発生する方法がとられている。たとえばその主
なものに、ダイオードなどのアナログ的な白色雑音源を
用い、これから取り出したアナログ電気信号をA/D変
換する方法、2進信号を自乗して中間のビットを抽出す
る方法、M−系列信号を用いる方法などがある。しかし
、最初の方法は回路構成が複雑になり、2番目の方法は
乗算や中間ビット抽出のためのプログラム処理が必要で
オーバーヘッドが大きくなり、そして最後の方法は直列
信号形式で乱数信号が得られるため、これを並列信号形
式に直並列変換する必要があり、速度が遅くなるという
ように、それぞれ大きな欠点をもっていた。
In the case of the above-mentioned example, in other measurement and data processing systems that require random number processing, a method is usually used in which random numbers are generated using pseudo-random numbers. For example, the main methods include a method that uses an analog white noise source such as a diode and A/D converts the analog electrical signal extracted from it, a method that squares a binary signal and extracts the intermediate bits, There are methods that use sequence signals. However, the first method requires a complicated circuit configuration, the second method requires program processing for multiplication and intermediate bit extraction, resulting in large overhead, and the last method obtains a random number signal in the form of a serial signal. Therefore, it was necessary to convert this into a parallel signal format from serial to parallel, and each had major drawbacks such as slow speed.

〔発明の゛目的および要点〕[Object and gist of the invention]

本発明の目的は、簡単な回路構成で高速に擬似乱数を発
生できる手段を提供することにあり、そのため、入力2
進信号中の所定のビット位置を入れ替える回路を設け、
一定の方向へ順次的に変化する入力2進信号系列を、同
一のデータ幅内で上下に大きくスイング変化する出力2
進信号系列に変換することにより、擬似乱数信号を得る
ものである。
An object of the present invention is to provide a means for generating pseudorandom numbers at high speed with a simple circuit configuration.
A circuit is provided to replace a predetermined bit position in the forward signal,
An input binary signal series that changes sequentially in a fixed direction is output with a large swing change up and down within the same data width.
A pseudo-random number signal is obtained by converting it into a hexadecimal signal sequence.

〔発明の実施例〕[Embodiments of the invention]

以下に、本発明の詳細を実施例にしたがって説明する。 The details of the present invention will be explained below based on examples.

第2図は、本発明の1実施例回路であって、分光光度計
に用いられる可変波長光源の波長制御回路を示したもの
である。図中、lはクロック発振器、2ばnビットカウ
ンタ、3は擬似乱数発生回路、4はラッチ回路、5はD
/A変換回路を表す。
FIG. 2 shows one embodiment of the present invention, which is a wavelength control circuit for a variable wavelength light source used in a spectrophotometer. In the figure, l is a clock oscillator, 2 is an n-bit counter, 3 is a pseudo-random number generation circuit, 4 is a latch circuit, and 5 is a D
/A conversion circuit.

nビットカウンタ2はクロック発振器lによって連続的
に駆動され、nビットのデータ幅内で順次的に変化する
並列2進信号、すなわち並列ディジタル信号を発生ずる
The n-bit counter 2 is continuously driven by a clock oscillator l and generates parallel binary signals, ie parallel digital signals, which vary sequentially within a data width of n bits.

擬似乱数発生回路3は、並列2進信号中のビット配列を
一定の規則で入れ替える回路である。ビ・7ト配列の入
れ替えは、入力と出力との間はビット線を交差接続する
ことによって行われ、人力された2進信号系列は、擬似
乱数化された2進信号系列となって出力される。ビット
配列の入れ替えの方法については後述される。
The pseudo-random number generation circuit 3 is a circuit that permutes the bit arrangement in a parallel binary signal according to a fixed rule. The permutation of the bit array is performed by cross-connecting the bit lines between the input and output, and the human-generated binary signal sequence is output as a pseudo-randomized binary signal sequence. Ru. The method of permuting the bit array will be described later.

ランチ回路4は、擬似乱数発生回路3から出力されたn
ピッ1−の擬似乱数化2進信号を1クロック期間だり保
持する。D/A変換回路5はランチ回路4内の擬似乱数
化2進信号をアナログ信号に変換し、図示されない可変
波長光源に供給される。
The launch circuit 4 receives n output from the pseudorandom number generation circuit 3.
The pseudo-randomized binary signal of P1- is held for one clock period. The D/A conversion circuit 5 converts the pseudorandom binary signal in the launch circuit 4 into an analog signal, which is supplied to a variable wavelength light source (not shown).

第3図は、擬似乱数発生回路3の構成例を示す説明図で
ある。本例は入力2進数のビットを上下2分割した場合
を示したもので、図(a)はnビットの入力2進数であ
り、最下位ビットをす、、最上位ビットをす、、、n/
2−mとして、〔b8.・・・+ bm + bl11
++ +・・・、b7〕 ・・・(1)で表される。図
(b)は、図(a)の人力2進数を2分割し、その(b
+ 、・・・、bLI)と(b、++、・・・、b7〕
を上下入れ替えたものであり、(bs+++・・・、b
、、b、、・・・、b1〕 ・・・(2)で表される。
FIG. 3 is an explanatory diagram showing an example of the configuration of the pseudo-random number generation circuit 3. This example shows the case where the bits of an input binary number are divided into upper and lower parts. Figure (a) shows an input binary number of n bits, where the least significant bit is 0, the most significant bit is 0, 0, n /
2-m, [b8. ...+ bm + bl11
++ +..., b7]... Represented by (1). Figure (b) shows how the human-powered binary number shown in figure (a) is divided into two, and then (b)
+ , ..., bLI) and (b, ++, ..., b7]
are reversed, and (bs+++..., b
,,b,,...,b1]...(2).

図(c)は、図(b)の下半分(b。Figure (c) shows the lower half of figure (b).

+1.・・・、bn)のピントを上下逆転したもので、
(bfi、・・・+ bm ++ + b+ + ・・
・、b、〕・・・(3)で表される。図(d)は、さら
に図(C)の上半分〔b5.・・・、b8〕のビットを
上下逆転したもので 〔bll、・・・+ bm ++ + b11+ ・・
・、b、〕・・・(4)で表される。
+1. ..., bn) with the focus upside down,
(bfi,...+ bm ++ + b+ +...
., b,]...(3). Figure (d) further shows the upper half of figure (C) [b5. ..., b8] with the bits upside down [bll, ...+ bm ++ + b11+ ...
・,b,]...It is represented by (4).

以上において、入力2進数(1)のビット配列を入れ替
えた(2)、(3)、(4)の2進数は、いずれも擬似
乱数として使用できるものである。
In the above, the binary numbers (2), (3), and (4) obtained by replacing the bit arrangement of the input binary number (1) can all be used as pseudo-random numbers.

このように本例によれば、入力2進数は上下半数のビッ
トを入れ替えられることによって、入力2進数における
下位ビットの本来の順次的な小さな変化は、入れ替えら
れた上位ビットにおいて拡大された大きな変化となって
現れる。
In this way, according to this example, by swapping the upper and lower half of the bits of the input binary number, the original sequential small changes in the lower bits in the input binary number become larger changes in the swapped upper bits. It appears as.

第4図は、n=4の場合についての上記した(1)乃至
(4)の各2進数構成を示したものであリ、第5図は、
その中で特に(1)と(4)をグラフで示したものであ
る。図示のように、(1)の入力2進数が0から15の
レベルまで連続的に単位変化していくのに対して、(4
)の出力2進数はOと15の間を大きくスイングしなが
ら変化する。
FIG. 4 shows each binary number structure of (1) to (4) described above for the case of n=4, and FIG.
Among them, (1) and (4) are especially shown in graphs. As shown in the figure, the input binary number in (1) changes continuously from level 0 to level 15, while (4
)'s output binary number swings widely between 0 and 15.

なお、第3図乃至第5図に示されている例は、人力2進
数のピントを上下2分割して入れ替えあるいはさらに上
下でビットを反転させたものであるが、本質的には、一
定数の下位ビットと上位ビットとを変換して、近接する
2進数間士の距離が大きくなればよく、そのためには、
さらに分割数を増やしてその間で種々の直接的あるいは
循環的な交差接続を行うことも可能である。第6図はそ
の1例を示したものであり、比較的ランダムな交差接続
を行ったものである。
In the examples shown in Figures 3 to 5, the manual focus of the binary number is divided into upper and lower halves and swapped, or the bits are further reversed in the upper and lower halves, but essentially, the focus is on a fixed number. The distance between adjacent binary numbers can be increased by converting the lower bits and upper bits of
It is also possible to increase the number of divisions and perform various direct or cyclic cross-connections between them. FIG. 6 shows one example, in which relatively random cross-connections are performed.

このようにして、第2図に示されている可変波長光源の
波長制御回路において、予定されたスペクトル領域の全
体を時間的に均一に掃引することができ、整時性が改善
される。
In this way, in the wavelength control circuit for the variable wavelength light source shown in FIG. 2, the entire predetermined spectral region can be temporally uniformly swept, and timing performance is improved.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明によればきわめて簡単な回路構成
により擬像乱数信号を生成することができ、かつそのた
めの時間遅れがほとんどないため、高速制御が可能とな
る。
As described above, according to the present invention, a pseudo random number signal can be generated with an extremely simple circuit configuration, and there is almost no time delay for this purpose, so high-speed control is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は掃引時間が吸収スペクトルに与える影響を示す
説明図、第2図は本発明の1実施例回路図、第3図は擬
似乱数発生回路の構成例を示す説明図、第4図は第3図
に示された例を4ビツトの2進数に適用した場合に得ら
れる2進数系列の説明図、第5図は第4図中の(1)お
よび(4)をグラフで示したもの、第6図は擬似乱数発
生回路の他の構成例を示す説明図である。 図中、1はクロック発振器、2はnビットカウンタ、3
は擬似乱数発生回路、4はラッチ回路、5はD/A変換
回路を示す。 特許出願人 新技術開発事業団 代理人弁理士 長谷用 文 廣 才Z肥 才3m ″j′今図
Fig. 1 is an explanatory diagram showing the influence of sweep time on the absorption spectrum, Fig. 2 is a circuit diagram of one embodiment of the present invention, Fig. 3 is an explanatory diagram showing an example of the configuration of a pseudorandom number generation circuit, and Fig. 4 is an explanatory diagram showing the influence of the sweep time on the absorption spectrum. An explanatory diagram of the binary number series obtained when the example shown in Figure 3 is applied to a 4-bit binary number, and Figure 5 is a graph showing (1) and (4) in Figure 4. , FIG. 6 is an explanatory diagram showing another example of the configuration of the pseudo-random number generation circuit. In the figure, 1 is a clock oscillator, 2 is an n-bit counter, and 3
4 indicates a pseudo random number generation circuit, 4 indicates a latch circuit, and 5 indicates a D/A conversion circuit. Patent Applicant: New Technology Development Corporation, Patent Attorney, Hase Yo, Text: HirozaiZ, Hizai3m ″j′Imazu

Claims (1)

【特許請求の範囲】[Claims] 順次的に大きさが変化する並列2進数を発生する手段と
、該発生された並列2進数の下位の所定のビットを上位
の所定のビット位置へ移動するビット配列変更を行う手
段と、該ビット配列変更された並列2進数を出力する手
段とからなる擬似乱数発生回路。
means for generating a parallel binary number whose size changes sequentially; means for changing the bit arrangement to move a lower predetermined bit of the generated parallel binary number to an upper predetermined bit position; A pseudo-random number generation circuit comprising means for outputting parallel binary numbers whose arrangement has been changed.
JP59059749A 1984-03-28 1984-03-28 Pseudo random number generating circuit Pending JPS60204032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59059749A JPS60204032A (en) 1984-03-28 1984-03-28 Pseudo random number generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59059749A JPS60204032A (en) 1984-03-28 1984-03-28 Pseudo random number generating circuit

Publications (1)

Publication Number Publication Date
JPS60204032A true JPS60204032A (en) 1985-10-15

Family

ID=13122196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59059749A Pending JPS60204032A (en) 1984-03-28 1984-03-28 Pseudo random number generating circuit

Country Status (1)

Country Link
JP (1) JPS60204032A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006238922A (en) * 2005-02-28 2006-09-14 Sankyo Kk Slot machine
JP2009233440A (en) * 2009-07-22 2009-10-15 Sammy Corp Random number generating device of game machine
JP2010194339A (en) * 2010-05-14 2010-09-09 Olympia:Kk Slot machine
CN111406247A (en) * 2017-11-28 2020-07-10 日本电气株式会社 Random number generation circuit and random number generation method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5382140A (en) * 1976-12-27 1978-07-20 Rca Corp Word bit rearraying circuit
JPS5494251A (en) * 1978-01-10 1979-07-25 Mitsubishi Electric Corp Operation unit for two dimensional orthogonal conversion
JPS54108546A (en) * 1978-02-13 1979-08-25 Toshiba Corp Converter for information array
JPS59160236A (en) * 1983-03-01 1984-09-10 Matsushita Electric Ind Co Ltd Pseudo random number generating device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5382140A (en) * 1976-12-27 1978-07-20 Rca Corp Word bit rearraying circuit
JPS5494251A (en) * 1978-01-10 1979-07-25 Mitsubishi Electric Corp Operation unit for two dimensional orthogonal conversion
JPS54108546A (en) * 1978-02-13 1979-08-25 Toshiba Corp Converter for information array
JPS59160236A (en) * 1983-03-01 1984-09-10 Matsushita Electric Ind Co Ltd Pseudo random number generating device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006238922A (en) * 2005-02-28 2006-09-14 Sankyo Kk Slot machine
JP2009233440A (en) * 2009-07-22 2009-10-15 Sammy Corp Random number generating device of game machine
JP2010194339A (en) * 2010-05-14 2010-09-09 Olympia:Kk Slot machine
CN111406247A (en) * 2017-11-28 2020-07-10 日本电气株式会社 Random number generation circuit and random number generation method
CN111406247B (en) * 2017-11-28 2023-10-10 日本电气株式会社 Random number generation circuit and random number generation method

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