SU976449A1 - Multi-dimensional static analyzer - Google Patents

Description

with S) MULTIDIMENSIONAL STATISTICAL ANALYZER

Claims (3)

The invention relates to computing and measuring technology and can be used in experimental studies related to multidimensional statistical analysis of correlated multidimensional random processes.  The well-known scheme of a multidimensional associative analyzer, whose work is based on the fact that a preliminary experiment is first carried out, in which the most probable events are revealed and recorded in the catalog, and then the main experiment, when using an associative memory device, an accumulation of statistical information occurs. preliminary experiment events With 1J.  This analyzer is characterized by relatively low rapidity, since the analysis time is increased due to the conduct of a preliminary experiment.  Closest to the proposed technical entity is a multidimensional statistical analyzer that contains an address register, a memory device, a control device, an arithmetic device register 1, an output device and a preliminary memory device, the information inputs of which are connected to the outputs of the random process realization sources, and the output with input address register, the output of which is connected to the address input of the storage device, the control input and the output of which are connected respectively venno with output and input of the control device, and data input and output - with a pen data output and data input register of the arithmetic unit 1, second information output kotg. . It is connected to the input of the output device 2. The disadvantages of this analyzer are inefficient use of memory and, as a result, complexity and low speed in analyzing multidimensional correlated processes.  The inefficient use of the memory of the analyzer is due to the fact that here the incoming information code serves as the address of the memory cell in which the histogram element is stored.  If the parameters of the random process being analyzed are related to each other by correlation dependences, then the number of different codes that entered the torus analyzer during the experiment will be much less than theoretically possible.  As a consequence, a significant portion of the memory cells will remain unused.  In addition, an increase in the dimension of the analysis leads to a sharp increase in the volume of the initial information, which makes it impossible to use high-speed operational storage devices for storing statistical information.  The use of mass storage devices, but with a low data access time, dramatically complicates the analyzer and reduces its speed.  The purpose of the invention is to simplify the analyzer and increase the speed. The goal is achieved that in a multidimensional statistical analyzer containing a preliminary memory, the informational inputs of which are the corresponding inputs of the analyzer, register the address, which output is connected to the address input of the memory unit, control inputs and the output to which are connected respectively to the forward control output and input of the control unit, the first information input and output of the memory unit are connected respectively to The first information output and the register input, the control input of which is connected to the second control output of the control unit, the second information output of the register is connected to the result output unit, and the third formation output is connected to the first bit address input of the address register; and a key-to-address conversion unit whose output is connected to the second bit input of the address register, and an input of the key-to-key conversion unit is combined with the second information input of the memory block, the first information The input of the collision resolution block is connected to the output of the preliminary memory, the control input of which is connected to the third control output of the control unit, the fourth control output of which is connected to the control input of the address register, and the fifth control output is the first control the collision resolution block input, the control output of which is connected to the second control input of the control block, the second information input and the first and second information outputs of the collision resolution block with Dineny respectively with the first information output of the memory unit, with the third bit input of the address register and with the second information input of the register, the ColLY permission block can consist of a comparison circuit and an overflow address register, the first and second outputs of which are the first and second information outputs block, the third output of the overflow address register is connected to the first information one. the input of the comparison circuit, the second and third inputs of which are respectively the first and second information inputs of the block, the output of the comparison circuit is the control output of the block, and the control input of the comparison circuit is combined with the control input of the overflow address register .  The key-to-address conversion unit can be configured as a multi-input adder and consists of a chain of serially connected memory, an adder and an address register, with the memory input being the input of the block and the output of the address register being the output of the block.  The control unit may consist of a chain of series-connected generator, counter and decoder, the control inputs of which are 537, respectively, the first and second control inputs of the unit, and the outputs of the decoder are respectively the control outputs of the unit.   FIG.  1 shows the proposed multidimensional statistical analyzer: in FIG. 2 is a block diagram illustrating the principle of operation of the analyzer; in fig.  3 is an example of the implementation of the control unit; in fig.  4 shows an example of a possible implementation of a key-to-address conversion unit when the key is split into three groups of bits; in fig.  5-9. - timing diagrams explaining the operation of the control unit.  The analyzer contains a preliminary storage device 1, the information inputs of which are the corresponding inputs of the analyzer, and the output is connected to the input of the key to address conversion unit 2 and the first information input of the collision resolution unit 3, the output of the key to address conversion unit 2 is connected to the second bit input of the register address, the output of which is connected to the address input of the memory block 5, the control input and the output of which are connected respectively to the first control output and the input of the block 6. control, the second control output of which is connected to the control input of register 7, the first information output and input of which are connected respectively to the first information input and output of memory block 5, and the second and third information outputs - respectively to output result block 8 and the first the bit input of the address register, the control input of which is connected to the fourth control output of the control unit 6, the third control output of which is connected to the control input of the preliminary memory 1, the output of which is connected to the second information input of the memory unit 5, the first information output of which is connected to the second information input of the collision resolution unit 3, the first and second information outputs of which are connected to the third digit input of the address A and the second information input the input of register 7, and the control input and output, respectively, with the fifth control output and the second control input of the control unit 6.  The collision resolution block 3 of the proposed analyzer may contain an overflow address register 9, the first and second outputs of which are the first and second information outputs of block 3, and the comparison circuit 10, the first information input of which is connected to the third output of the overflow address register 9, and the second and third the inputs are the first and second information inputs of block 3, respectively.  the output of the comparison circuit 10 is the control input of the unit 3, and the control input of the comparison circuit 10 is combined with the control input of the overflow address register 9 and is the control input of the unit 3.  The key-to-address conversion unit 2 may be made up of a multi-input adder and consist of a chain of memory device 1 connected in series, adder 2 and address register k, the input of memory 1 being the input of the block, and turning on register A of the address is output block.  In addition, the control unit 6 can be made in the form of a chain of series-connected generator 11, counters 12 and a decoder 13, the control inputs of which are the first and second control inputs of the block, respectively, and the outputs of the decoder 13 are respectively the control outputs of block 6 .  The principle of operation of the proposed multidimensional statistical analyzer is based on the use of a certain non-linear function, which forms the addresses of the memory blocks in a given range. Depending on the source.  representing one implementation of a random process.  The key entering the analyzer uses a nonlinear function to generate the address of the memory location corresponding to the key.  If this cell is free, then a key is written into it.  Cell with address.  assigned to generate a key histogram, m. e.  its content is increased by one.  This completes the processing of this key.  If the cell with the address A is found to be occupied, the analysis is performed for the equal of the current key and the key previously written in this cell.  When they coincide, the histogram at address A is reached, and processing of the current key value is completed.  If the match does not match, when different keys are addressed to the same cell, the special scheme generates a new A value for the current key, after which the cell content with address A is repeated. This procedure is repeated until No cell will be found storing this key either free / On average, 1-2 key times are required to place any key.  At the end of the experiment, when the memory is full, the results are output to the external medium. The multidimensional statistical analysis of the torus works as follows.  The signal generated at the third control output of control block 6 allows recording the numeric code entered at the input of the analyzer from external sources of implementations, the size of which depends on the dimension of the process being analyzed in preliminary memory (Fig.  5) - Block 2 to convert the key to an address by means of a nonlinear transform of a key. generates the address of the opening of the flash memory cell 5, in which this key should be stored.  The operation of the key-to-address block 2 may proceed as follows.  The key, which is a digital binary code, enters an interim storage device which can be made in the form of a register.  The outputs of the preliminary storage device, 1, are divided into groups according to n bits, where n is determined by the size of the main memory area equal to 2, into which the keys are initially addressed.  The adder 2 performs the operation of adding the corresponding bits of the different output groups of the preliminary storage device 1 and the result is stored in the address register, the bit size of which is n.  If the total number of bits of the pre-storage device 1 is not a multiple of n, then the latter group with the number of bits less than n, conditionally complements to the stubs and participates in the operation of adding together with the rest of the groups of bits.  The signal of the fourth 9 control output of the control block 6 permits the writing of the address generated by the key-to-address block 2 to the address register k on the second bit input.  The register register address k is smaller than the preliminary storage device 1 and corresponds to the size of the main memory area in which the statistical information is stored.  Then, control unit 6 generates signals at the first and fifth control outputs.  In this case, the memory block 5 is addressed to the address stored on the address register k, and the contents of this cell, which is fed to the second information input of the comparison circuit 10, is analyzed in the maintenance circuit of the collision resolution unit 3.  If the cell is free, the comparison circuit 10 generates a signal at the output that arrives at the second control input of the control unit 6, which in turn generates signals at the first and third control outputs, thereby allowing the rewrite of the current key to this memory cell 5 on the second information entry.  In the next cycle of operation, the signal at the fourth control output of control unit 6 increases by one the contents of the address register k.  Then, the contents of the cell having the newly formed address, with the supply of permissive signals on the first and second control outputs of control unit 6, are rewritten to register 7, increased by one in the next clock cycle, and then stored again in memory block 5 at the same address.  In this way, a histogram is generated for a given key.  Processing is over and the analyzer is ready to receive the next key.  If, as a result of the analysis in block 3, the resolution of collisions occurs, the cell is occupied, t. e.  on the fourth such a signal on the second control. the input of lock 6 control is absent (FIG. 6), in the next cycle, the control unit 6 arranges the signals on the first, third fifth control outputs.  At the same time, the key stored in this cell sinks to the second information input comparison chapter 10, the first information input of which receives the current key from the output of the preliminary storage device 1.  When these keys coincide, the circuit 10, as compared to the output, generates a signal, which is supplied to the second control input of the control unit 6.  Starting from the seventh clock cycle, the processing is similar to the case described above: the contents of the address register 4 are incremented by one and so on. d.  If the last check reveals key inequality, t. e.  the signal at the second control input of the control unit 6 in the sixth cycle is absent (Fig.  7), the cell address of the memory 5, which is allocated for storing the current key, is generated by the collision resolution block 3.  This can be implemented as follows.  Each element of the histogram contains three cells: the first stores the second key — the histogram of this key, respectively; a third — the address of which key, which should be addressed to place the current key when a collision occurs.  In this case, the work is as follows.  one -.  Control unit 6 generates two additional signals at the fourth control output, which increase by two the contents of the address register.  Then, in the presence of signals on the first and second control outputs of control unit 6, the contents of the cell with the newly formed address, which in turn is the address, is rewritten to register 7 at the first information input. which should be addressed to place the current key in a collision.  In the following cycle, this address is analyzed in comparison circuit 10.  If it is different from zero, this means that a collision had previously occurred in this cell.  In this case, the comparison circuit 10 in the eleventh cycle generates a signal at the second control input of the control unit 6, according to which it then sets the signals at the second and fourth control outputs, which causes the contents of register 7 to be copied to the address register k. Then, the control unit 6 allows the comparison circuit 10 to compare the current key received at the first information input and the key stored in the cell with the newly formed address coming from memory 5 to the second information input. Further work is similar to that described above, starting from the sixth tact  If the address extracted at the tenth step is zero, t. e.  the signal at the second control input of the control unit 6 is missing in the eleventh cycle (Fig.  8), this means that earlier no collisions occurred in this cell and the placement of the current key in the analyzer memory is assigned to the collision resolution block 3.  This may occur as follows. The key is addressed to an additional memory area starting with some predetermined address.  The dimensions of this additional area are from the main storage area.  The control unit 6 generates signals on the second and fifth control outputs, which causes a copy of the address of the first free cell of the additional memory area stored in register 9 of the overflow address to register 7.  This address is then stored on signals in the first and second control outputs of control unit 6 in a cell of memory block 5, whose address is currently stored in the address register.  In this way, communication is established between keys that have been addressed to the same cell.  In the next cycle, the contents of the register 9 of the overflow address on the third bit input enters the register 4 addresses and, at this new address, the key from the preliminary memory is written to the memory block 5.  va 1.  Then the address in the address register t by the signal at the fourth output of control unit 6 is incremented by one.  After this, histograms are completed, for which the contents of the cell with the newly formed address is extracted to the register 7 by a signal at the second control output of the control unit 6 is increased by one and then stored again in the memory block 5 at the same address.  In the next step, in order to ensure that the incoming keys are effectively placed, it is necessary to form the address of the first free cell in the additional memory area where a new collision could have been posted. For this purpose, the contents of the overflow address register 9 at the second control output of the control unit 6 is increased by three.   When going beyond the limits of the discharge grid of the register 9, the overflow address at the second control input of the control unit 6 is formed. -. a signal that indicates that the additional memory area is completely naught and no new, t. e.  previously not met, the keys can no longer be placed with.  In this case, you can either stop the experiment, or continue the accumulation of statistical information about the keys already received.  At the end of the experiment, in order to display the results for the operator, block 6, in turn, in the preliminary storage device 1, sequentially generates the codes of all possible keys (Fig.  9) .  Of these, the key-to-address conversion unit 2 forms the cell addresses of the memory block 5, in which the corresponding histogram elements are stored.  This information is retrieved to register 7, from where it arrives at block 8, the output of the cut.  Thus, the effective use of memory allows you to simplify and increase the speed of the analyzer.  Claim 1. The multidimensional statistical analyzer containing the preliminary memory, the information inputs of the second are the corresponding inputs of the analyzer, the address register, the output of which is connected to the address input of the memory unit, the control input and output of which are connected respectively to the first control output and the control unit , the first information input and output of the memory unit are connected respectively to the first information output and the input of the register, the control input of which is connected to the second control the second information output of the register is connected to the output output unit, and the third information output to the first bit input of the address register, characterized in that, in order to simplify the analyzer and improve speed, a collision resolution block and a block are entered into it converting, / calling the key into the address whose output is connected to the second bit input of the address register, and the input of the key converting block to the address is combined with the second information input of the memory block, the first information center 1 known input block collision resolution and is connected to the output of the preliminary storage device, the control input of which is connected to the third control output of the control unit, the fourth control output of which is connected to the control input of the address register, and the fifth control output - to the first control input of the block collision resolution, the control output of which is connected to / to the second control input of the control unit, the second information input and the first and second information outputs of the collision resolution block are connected respectively etstvenno with. the first is the information output of the memory block, with the third bit input of the address register and with the second information input of the register. .   2. The analyzer of claim 1, wherein the collision resolution unit consists of a comparison circuit and an overflow address register, the first and second outputs of which are the first and second information outputs of the block, the third output of the overflow address register is connected With the first information input of the comparison circuit, the second and third inputs of which are respectively the first and second information inputs of the block, the output of the comparison circuit is the control output of the block, and the control input of the comparison circuit is combined with the control input home address register overflow and is a control input of Adim. 3. The analyzer according to claim 1, of which there is a tachograph: so that the key-to-address conversion unit is designed as a multi-pass sumMaTopa and consists of a chain of memory devices connected in series, an adder and an address register, the memory input is the input of the block, and the output of the address register is the output of the block. k. The analyzer according to claim 1, wherein the control unit consists of a chain of series-connected generator, counter and decoder, the control inputs of which are respectively. AND YU Phi2 / 9 the first and second control inputs of the block, and the outputs of the decoder are respectively the control outputs of the block. Sources of information taken into account in the examination 1. S. Kurochkin. Multidimensional statistical analyzers. M., Atomizdat, 1968, p. ZP 2. The same. with. 11 (prototype). FIG. 2 G End J I tCt3u .S 2n Fy  1 8 9 10 f 2 physical b tN4 “§ FROM) About CV4 I I