JPS5827438Y2 - shift register - Google Patents

Description

[Detailed Description of the Invention] The present invention particularly relates to a shift register circuit with a large capacity and whose storage capacity can be set appropriately.

In general, in grinding equipment that processes the same product continuously, in order to control the processing status and check the processing precision of the grinding equipment, it is necessary to check the occurrence of defective products for the total number of processed products or for a sampling unit. A defective product ratio monitoring device is used to monitor the ratio.

This defective product ratio monitoring device stores a predetermined number of good/defective judgment data for each crushed product, updating the oldest data one by one with the latest data. The defective product ratio is calculated from a predetermined number of good/defective judgment data and is used as monitoring data or control data.

The storage section of this defective product ratio monitoring device generally uses a large-capacity shift register in which the number of data stored can be set in response to changes in the number of sampling units.

Such shift registers include, for example, N shift registers 1-1, 1-2, etc., as shown in FIG.
A serial shift register configuration is adopted in which l-n are connected in series.

In the figure, 3 is a timing clock generation circuit that sends a shift input timing clock to each shift register 1 using a data manual clock, and 4 is the number of valid judgment data to be stored in the serial shift register, that is, the total minimum memory of shift register 1. A register capacity setting section sets the minimum number of storage units for effectively storing data contents among the number of units using a BCD code. 5 is a code that converts the BCD code set in the register capacity setting section 4 into a BINARY code and outputs it. This is the conversion section.

2 is a data sector Vctor that selectively outputs the parallel outputs of each shift register 1, and the selected range, that is, the data stored in the smallest storage unit among the data contents sequentially stored in shift register 1. Whether the code is output is determined by the number set in the register capacity setting section 4 which is converted into a BINARY code by the code conversion section 5.

This set number determines the effective storage capacity of the shift register 1, that is, the register capacity.

By the way, the above conventional configuration has the following drawbacks.

For example, create a large-capacity serial shift register with 1 bit f
f, if one shift register 1 is 8 bits, 125 /8 is required, and if it is 4 bits, 250, twice that number, must be connected in series. No.

Therefore, as the capacity increases, the conventional system described above has the disadvantage that the soft register 1 and data selector 2 become enormous, making them expensive and large.

The present invention improves and eliminates the above conventional drawbacks, and uses RAM (semiconductor READ WRITE) instead of a plurality of shift registers 1 connected in series as storage elements.
Instead of the data selector 2 that selects and retrieves stored data, a program counter that specifies read and rewrite addresses is used to create something similar to multiple shift registers connected in series. RAM is used to increase storage capacity as a register.
In order to increase the memory capacity of the memory and increase the number of digits of the program counter, we also implemented a shift register circuit incorporating a control section consisting of a register capacity setting section, etc., to make it easier to set and change the number of data stored. provide.

Hereinafter, the configuration of the present invention will be explained with reference to the drawings.

In FIG. 2, 6 is the above-mentioned RAM, 7 is a program counter, S is a control section, 8 is a timing clock generation circuit, 9 is a register capacity setting section, 10 is a code conversion section, 11
1 is a comparison circuit, and 12 is a gate circuit (AND circuit).

RAM6 uses data to determine whether the product is OK or bad.
) etc. are stored.

Then, the program counter 7 reads the address of the RAM 6 (
This is a counter for indicating the address (address), and is incremented by one each time the data clock arrives.

Also, RAM6 stands for random access memory.
Timing clocks B and C from the timing clock generation circuit 8 are used for this operation in order to read and rewrite the stored contents at arbitrary addresses.

This timing clock generation circuit 8 generates four types of timing clocks A, B, C, and D as shown in FIG. 3 using the data input clock.

The first timing clock A is a gate circuit (A
ND circuit) 12, the next timing clocks B and C are R
At AM5, the last timing clock D is input to the program counter 7, which causes the respective operations to be described later.

The register capacity setting section 9 arbitrarily sets the shift register capacity, that is, the number of data contents to be stored in the RAM 13, in accordance with the number of sampling units, etc. using a BCD code,
The code conversion section 10 also converts the BCD code set by the register capacity setting section 9 into a BINARY code so that it can be compared with the contents of the program counter 7.

Further, the comparison circuit 11 is a circuit that compares the value set by the register capacity setting section 9 and the contents of the program counter 7, and subtracts the contents of the program counter 7 from the register capacity setting value converted into a BINARY code. The complement of the contents of the counter 7 is added, and if there is a carry, it is a plus, if there is no carry, it is a minus or zero, and a match signal is taken out. If timing clock A arrives when they match, the program counter is This circuit clears the contents of 7.

For example, if the setting value of the register capacity setting part 9 is 536, this is 01010011 from the upper digit in the BCD code.
0110, and if this is converted into BINARY, it becomes 1000011000.

Therefore, the contents of program counter 7 are also 536,
If the BINARY code is 1000011000, set it to 1 to compare it with the register capacity setting value.
Taking the complement of 000011000 is 011110011
1 becomes 1000011000+0111100111=111
1111111, there is no carry, and a match signal is output at this time.

If the lid register capacity setting value is the same as 536, but the contents of program counter 7 are different from 535, 535 is BINA.
The RY code is 1000010111, and its complement is 0111101000, so it is 1000011000.
+0111101000=10000000000, 1 appears in the 11th digit, there is a carry, and at this time no match signal is output.

Next, the operation of the above circuit using timing clocks A, B, C, and D will be explained.

As shown in Figure 3, timing clocks A, B, C, D
divided into time 11.12.13.14 by time t
1 is timing clock A, time t2 is the NO level of timing clock B and timing clock C, time t3 is the high level of timing clock B and low V level of the timing clock, and time t4 is taken out by timing clock D. This will result in the following behavior.

First, when the timing clock A is generated with the contents of the register capacitance setting section 9 and the program gate tough matching and a match signal being output from the comparison circuit 11, a clear signal is sent from the gate circuit (AND circuit) 12. It is output to the counter 7, clears the program counter 7, and causes the program counter 7 to specify, for example, address O in the RAM 6.

Next, at time t2 between timing clock B and timing clock C, the contents of the RAM 6 addressed by the program counter 7 (address O at the above point in time) are read out and taken out from the data output. At time t3, the contents of the address in the RAM 6 specified by the program counter 7 (address O at the above point in time) are rewritten to the contents of the data manually.

Finally, at time t4 of the timing clock D, the program counter 7 is incremented by one.

Thereafter, the operation of reading and writing the data contents while sequentially updating the address of the RAM 6 is repeated until the program counter 7 matches the contents set by the register capacity setting unit 9.

Note that the timing of timing clocks A, B, C, and D is not limited to the example shown in FIG. ．． 12113.1
As shown in 4, the data may be extracted starting from the signal timing for clearing the program counter I, followed by the timing for reading and rewriting RAM data, and then the signal timing for increasing the counter of the program counter 7.

As explained above, in the present invention, the serial shift register is constructed using a RAM and a program counter, so that the register capacity can be easily increased.

In other words, RAM semiconductor memory has about 100 times more integration density than conventional shift registers, so increasing memory capacity as register capacity increases is much more advantageous than increasing the number of shift registers. becomes.

Also, while the increase in the number of digits in the program counter is an exponential increase, the increase in the shift register is a linear increase.As the memory capacity increases, the increase in the number of digits in the program counter is more This is advantageous compared to increasing the number of selectors.

Furthermore, in the present invention, the number of data storages (shift register capacity) can be arbitrarily set using the register capacity setting function of the control unit S, so that the memory element can be set to match the number of data storages (for example, the number of sampling units of processed products). R with the number
It can be used even if it is not an AM, and even if the number of data stored above changes depending on the processing object, it can be handled by simply adjusting the number set in the register capacity setting section, making it a versatile large-capacity shift register. can be provided at low cost and in a small size.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional serial shift register, Figure 2 is a block diagram of a conventional serial shift register.
The figure is a block diagram showing an implementation column of the shift register according to the present invention, and FIG. 3 is a time chart of clock waveforms at each point in the second embodiment. 6...RAM, 7...program counter, S...control unit.

Claims (1)

[Scope of utility model registration request] RAM (semiconductor REA DWRI) that stores data contents
TE MEMORY) and a program counter that specifies the address of the RAM, the shift register has a register capacity setting section that sets the number of data contents to be stored in the RAM, and a register capacity setting section that sets the count number of the program counter and the register capacity setting section. A comparison circuit that compares the set number and outputs a match signal when they match, and a timing clock that outputs, in this order, a timing clock for clearing the program counter, a timing clock for reading and rewriting RAM, and a timing clock for counting up the program counter. Consists of a clock generation circuit and a gate circuit that outputs the coincidence signal output from the comparison circuit to the program counter as a clear signal when the timing clock for clearing the program counter output from the timing clock generation circuit is generated, and sets the registration capacity appropriately. Outside the shift register, which is characterized by being equipped with a control unit that allows