JPS59127298A - Shift register - Google Patents

Abstract

PURPOSE:To remove the limit of the operation speed of an RAM, to reduce the power consumption, and to use an inexpensive RAM by converting input data from serial to parallel temporarily, and converting the operation speed into a speed lower than the maximum operation speed of a memory and then accessing the RAM. CONSTITUTION:Data inputted from a data input terminal A is inputted to a serial-parallel converter 3 according to a clock inputted successively from a clock input terminal B. The clock from the clock input terminal B is frequency- divided by four through a 1/n frequency divider 5 to perform clock conversion. The output of this 1/n frequency divider 5 is inputted to the RAM6 as its read/ write control signal and also is inputted to an address counter 7 as its counting clock. The RAM6 reads data out of an address of the RAM6 specified by the address counter 7 at the rising of the output of the 1/n frequency divider 5 and the stored data is outputted to a parallel/serial converter 4 in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of the Invention The present invention relates to a shift register which can be constructed in a small and compact manner, and which is capable of processing a number of commercial operations.

(1)) Prior art and problems The conventional shift register will be explained with reference to FIGS. 1 to 3.

FIG. 1 and FIG. 3 are diagrams showing an example of the configuration of a conventional shift register. In the figure, 1 is high-speed RAM (
Random Accedays Me+nory),
2 is an address counter, +lI''Fl to FF4 are D-type 7 logic flops (hereinafter referred to as free logic frogs),
A is a data input terminal, B is a clock input terminal, and C is an output terminal.

FIG. 2 is an explanatory diagram of the operation of FIG. 1, and (a) to (d) in the figure correspond to waveforms at points ta) to (d) in FIG. 1,431, respectively.

First, the 4-bit shift register shown in FIG. 1 will be explained.

The address counter 2 counts by "1" at the rising point of the clock shown in FIG. 2(b) which is manually inputted from the clock input terminal B, but the counted value is 0 to 1 as shown in FIG. 2(C). 1@ mouth 3″.

The = value of address counter 2 is used as the write address and read address of the high speed RAMI.
It's being crushed by M1.

High speed 1 (AM 1) is the rising of the clock manually input from the clock input terminal B, and the data input terminal A shown in FIG.
Insert the data from J. In addition, the speed f (AMI is the output of the clock manually inputted from the clock input terminal B, and the data inputted to the address position from the address counter 2 by the above operation. put out.

That is, in this case, as is clear from FIG. 2, a 4-bit shift register 'ft is constructed. In addition, if you want to configure an 8-pit shift register k with the configuration shown in Figure 1, the upper limit for one counting shift of address counter 2.
8” should be installed.

As other shift registers, there is one in which Norig frogs F'FI to FF'4 are connected in multiple stages, as shown in Figure 3. The shift of this shift register is determined by the stages of clip-on lags connected in multiple stages.

However, such a conventional shift register uses a high-speed RAM in order to perform high-speed excitation, and has the disadvantage that the high-speed 1 (AM) has a large readout force.

one! In addition, the shift register shown in Fig. 3 has the disadvantage that the structure is similar to that of Inushiro, and even more so, since the free-lag frogs are connected in multiple stages.

(C) Purpose of the Invention In view of the drawbacks of such conventional shift registers, the present defense provides that:
It is an object of the present invention to provide a shift register that is small in size, can be configured to have both sides, and is suitable for high-speed Otani winds.

td) Structure of the Invention In order to achieve the above object, the present invention provides serial/parallel converting means for converting n-bit serial/parallel data according to a human-powered data clock, and a lock frequency dividing unit 1/n. /n frequency division 4. A counting means inputting the output of the 1/n frequency divider and performing a sequential counting operation, according to the output of the 1/n frequency divider, the i
The output of the middle stage of mounting/parallel conversion is stored at the address indicated by the count value of the t number means, and the data meeting, parallel, etc. stored at the address indicated by the counting means according to the output of the d1/n frequency divider is A unique element outputting to the serial conversion means.

The shift register is characterized in that it has means for sequentially outputting data from the unique element in accordance with the clock.

te) From the embodiment of the invention, FIG. 4 shows one result of the uninvented shift register!
This will be explained in detail using the fPJ5 diagram. Note that the description will be made here for an 18-bisotonft register eN.

FIG. 4 is a block diagram of an embodiment of the shift register according to the invention. In the figure, 3 is a serial/parallel converter.

4 is a parallel/serial converter, 5 is an l/n frequency divider, and 6 is a RAM.

7 is an address counter.

FIG. 5 is an explanatory diagram of the I assistant in FIG. 4, and (a) to (g) in the same figure are 0 data input terminals corresponding to the waveforms at points (a) to (g) in FIG. The data shown in FIG. 5(a) manually input from A is sequentially input manually from clock input terminal B in FIG. 5(b).
) is manually input to the serial/parallel converter 63. Here, the serial/parallel converter 3 is constituted by a 4-bit shift V register, and outputs the serial data shown in FIG. 5(a) in parallel data of 4 bits each. In other words, the data rate is 1/4 of the human data rate.
You will be destroyed.

In addition, from the clock input terminal B, it is also possible to manually input the clock input terminal B as shown in FIG.
The clock shown in 1)) is divided into 1/4 by the 1/n frequency divider 5
The frequency is divided and the clock is converted as shown in FIG. 5(C). Then, the output of this l/n frequency divider 5 is inputted to the RAM 6 as a continuous output/increase control signal for the RAM 6, and is inputted to the address calantara as a counting clock for the address calantara.

In the address calantara, the output of the 1/n frequency division a5 (Fig. 5 (C)) is counted in the vertical direction, and the counting is performed in the first shift:
ii (Output as the address of AM6. Here, it is assumed that the address counter counts 0 to 3" once.

In the RAM 6, at the rising edge of the output of the manually operated l/n frequency divider 5, the j value stored at the address added by the address counter is output as shown in FIG. 5(f). , and outputs the stored data (!-parallel/serial conversion) to the actual output 4. In addition, the RAM 6 outputs the stored data (!-parallel to serial) to the address counter at the start of the output of the input 1/n frequency divider 5. t
The 4-bit data fc of the serial/parallel converter 3 is loaded into the address jtM as shown in FIG.

The 1 data input to the sub-serial converter 4, such as C1, are sequentially outputted from the output terminal C according to the clock in FIG. 6(b), as shown in section 51(g).

In other words, the output of this K-column reward device 4 (Fig. 5 (g)
) is the same speed as the human data shown in Figure 5(a),
Output to the outside.

Here, we will explain the 18-bit shift register, but the number of shifts is based on the 50 frequency division ratio of the 1/n frequency divider and the setting of the address counter.

Various choices can be made by arbitrarily setting the shifts of the series/parallel 3A, the converter 3, and the sub-series/series converter 4, and tltn.

(f+ Effects of the Invention As explained in detail above, in the shift register of the present invention, the input data is converted to a value lower than or equal to the highest or false operating speed of all memories by changing the input data to the maximum or false operating speed. wheat, flA
Since there is no limit to the operating speed of the flAM, the eraser viewing force is small, and one ton of new RAM can be used. In addition, the output data of the shift register can be outputted at the same speed as the input data.

[Brief explanation of the drawing]

1 and 3 are diagrams showing an example of the configuration of a conventional shift register, FIG. 2 is an explanatory diagram of the operation of FIG. 1, and FIG. 4 is an embodiment of the shift register of the present invention. FIG. 5 is an explanatory diagram of the operation of FIG. 4. In the figure, 1 is a pigeon speed RAM, 2 and 7 are address counters, 3 is a serial/parallel converter, 4 is a parallel/serial converter, 5
tB 1/n frequency divider, 6 is RAM, FFI to F'F4
1'il)/n flip-flop, A is the data input terminal, B is the clock input terminal, C is the output terminal, and F7
Figure 2 Figure 3 Figure 4 Procedure amendment form) Dear Director-General of the Licensing Agency, 1, i (I'l, 2j - 1977 'l?, t'j' is the judgment number) attached acos:
3,) + lil mino 15 go tl thing 1'l leap 1 i ↑Y, i'1 out) 11
Person 1 (111 ha God 4, Yoken Kawasaki Yamanaka 11; fl<
l: □I・Ill 1015 city area (522) n1 (ro,
Fujitsu Limited 4th Director f) 1st 1-11 Rikyo-ku 1-111 Junior High School 10157B 578-, Yozaki City, Kanagawa Prefecture

Claims (1)

[Claims] Serial/parallel conversion means for converting n bits into serial/parallel according to a total clock of human data, a 1/n frequency divider that divides the total frequency of the clock by 1/n, and an output of the 1/n frequency divider. +3m with full strength
According to the output of the 1/n frequency divider, the output of the serial/parallel conversion means is recorded at the address indicated by g1', so 1 direct of the counting means. ,
An H self-storage element that outputs the data stored at the address indicated by the counting means according to the output of the 1/n frequency divider to a stage for parallel/serial conversion. It has ten parallel/series stages that sequentially output data from the unique element according to the clock.
Shift register k.