SU1635206A1 - Adaptive telemetering device - Google Patents

Description

(21) 4677220/24

(22) 03.22.88

(46) 03/15/91. Bul Number 10

(71) Moscow Institute of Civil Engineers of Api

(72) S.Zh.Kishsens-kiy, V.E.Ignatiev, A.Ya.Kreker and V.A.Reshetnikov

(53) 621.398 (088.8)

(56) USSR Copyright Certificate No. 1492361, cl. C 08 C 19/28, 1987.

(54) ADAPTIVE TELEMETRIC DEVICE

(57) The invention relates to telemetry and computing and can be used to process compressed messages. The aim of the invention is to improve the speed by adjusting the parameters of the device to the statistics of the input information. The device contains a coefficient input block 1, a buffer memory block 2, a counter 3, an OR 4 element, a program-time block 5, the first and second blocks 6 and 10 of code comparison, the coefficient memory block 8 and the coefficient number memory block 9, a register 11 addresses, encoder 12, key block 13, shaper 14 module of the number, adder 15 and block 16 of comparison, first and second switches 7 and 19, first and second blocks 17 and 18 of memory, trigger 21 and divider 20. 2 Il.

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The invention relates to telemetry and computing and can be used to transmit and process compressed messages.

The aim of the invention is to improve the speed by adjusting the parameters of the device to the statistics of the input information.

FIG. 1 shows a block diagram of an adaptive telemetry device, FIG. 2 is a block diagram of a program-time block. The adaptive telemetry device (Fig. 1) contains a block 1 for inputting coefficients, a block 2 for buffer memory, a counter 3, an element OR 4, a program-time block 5, a first block 6 for comparing codes, a first switch 7, a block 8 for memory factor - cents, block 9 of memory of addresses of coefficients, second block 10 of code comparison, register 11 of address, encoder 12, block 13 of keys, driver 14, number module, adder 15, block 16 of comparison, first and second blocks 17 and 18 of the main memory, second switch 19, frequency divider 20, T-flip-flop 21, information inputs 22, initial input 23 installations, information outputs 24, tolerance signal bus 25.

Program-temporary block (figure 2) contains a generator 26 clock pulses, the first and second elements AND 27 and 28, the element OR 29, the trigger 30, the third element OR 31, the second trigger 32, the fourth element OR 33, the register 34f second counter, the fifth element OR 36, the first comparison element 37, the third counter 38, the second comparison element 39, the test element OR 40, the fourth counter 41, the decoder 42, the seventh element OR 43, the eighth and ninth elements OR 44 and 45.

The device works as follows.

The process of ordering the coefficients is divided into two steps. At the first stage, the coefficients are sorted into a number (N) of non-overlapping groups by size, each coefficient retaining its number in the common sequence. At the second stage, the coefficients are arranged within each group (for each group, the first and second

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ordering levels, starting with the group in which the coefficients with the highest values are collected, and so on, as the values of the coefficients decrease and in the corresponding groups. Such an order of ordering the coefficients within the groups makes it possible to efficiently order the coefficients of the entire array as a whole.

The division of the mass of the coefficients into groups is carried out by comparing them with a number of so-called code windows. Depending on the values of the selected code windows, the sizes of the coefficient groups are found. The choice of code window values in such a way as to achieve the maximum possible equality of the number of coefficients in all groups, and the main difference of the proposed device from the prototype consists. The maximum speed is achieved by organizing n groups of / n coefficients in each (i.e., Yn N), where n is the number of coefficients in the total array of decomposition.

When arranging the array of decomposition coefficients, the entire array of coefficients is first compared with the first (maximum in value) code window. The decomposition coefficients, the values of which are larger than the value of the first code window, constitute the first group. After selecting this group from the array of coefficients, the coefficients of the group inside the group are ordered and output to the recipient in descending order. Then, the remaining coefficients are compared with the value of the next (second largest) code window and the second group is selected, processed similarly to the first, and so on.

The termination of the next cycle of the device operation occurs in two cases:

when outputting all the coefficients of the array to the output of the decoder;

when the comparison unit triggers, recording the fact that the required conversion accuracy has been achieved.

The initial state of the device is set either by the initial setup signal at input 23, or upon completion of work in the next cycle of signals from block 16. These signals are sent to element 44 of block 5 and set

Trigger 30 (through element 29), trigger 32 (through element 31), counter 35 and 38 (respectively through elements 36 and 40) and counter 41 are returned to the initial state. With this signal from the fourth output of block 5, the counter 3 is reset , and the signal passed through the element 45 to the seventh output of block 5, - the address register 12. During the initial installation, the first and second memory blocks are also reset, and the initial values of the code windows are optionally written to them.

user The sets of initial values of code windows recorded in the first and second blocks of memory (they are designed to store these values: first, the original, and then the current) are identical. The trigger 21 can be in any initial state, it determines which of the blocks 17 and 18 of the memory is connected by the switch to block 6, while in this conversion cycle this block is the source of code window values, the second block at this time writes the values of the code windows that will be used in the next cycle. The trigger 30 determines the operation mode of the device in the time interval when this trigger is in the zero state, the device records the array of coefficients through block 1 into block 2. With the single state of trigger 30, the device operates in the ordering mode of the array of coefficients. Trigger 32 determines the current ordering level: when it is in a single state, the first ordering order is implemented — extracting a group of coefficients from an array by comparing them with the current code window, and when zeroing, the second ordering level of coefficients within the group and issuing them to the recipient. In the proposed device, in comparison with the prototype, during the second stage of the ordering, the determination of the current values of the code windows, which are used in the next conversion cycle, is carried out.

After the circuit has been reset, the signal from trigger 30 (from the inverse input) on the fifth output of block 5 enters block 1 and allows the expansion coefficients 35206 to pass.

block (total array) in block 2. Simultaneously with the formation of the next coefficient, block 1 generates a pulse, which through the element OR 4 goes to the counting input of counter 3 and sets the next (starting from zero) multi-bit address, at which block 2 records the JQ value corresponding coefficient. This address is the number of this decomposition coefficient (in the general array), which will further accompany this coefficient until it is issued to the recipient. The capacity of counter 3 is equal to the number of coefficients being formed (their number for all device operation cycles is constant and equal to n, as a rule, this number is a power of two). F

Simultaneously with the recording of the coefficients in block 2, they are compared with the first (maximum) sign.

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the code window and the selection of the first group of coefficients with the highest values, i.e. sifting the array of coefficients through the first code window, in the case when the value of the next coefficient is greater than the value of this code window (the comparison is made in block 6f, the value of the next coefficient coming from block 2, and the value of the code window from one of the memory blocks 17 and 18 through the first switch 7, which is defined by the signals from trigger 21), block 6 generates a signal that

entering into the coefficient memory unit 8, allows writing this coefficient into it, “

entering the memory of the coefficient numbers, allows the number of this coefficient to be written to it in the general array,

entering into block 2, zeroed the value of this coefficient (in order to exclude the further fate of this coefficient in the ordering process of the array),

acting in block 5 on the first input through the element OR 33, increases by one the contents of the counter 35.

The counter 35 generates an address at which the current coefficient of the group and its number are written to blocks 8 and 9, respectively (at the first output of block 5).

After recording in block 2 of the entire array of coefficients (p) and simultaneously allocating them to the first group (size n), counter 3 issues a signal to block 5 on the fourth output and sets trigger 30 to one, trigger 32 to zero, and gives the enabling signal for recording the number n, (, the form of the clock is compared to the second coefficient coded at this time into the counting group and the first coefficient. With the hook 35, into the storage register 34, each clock of the counter 35 has the address of the coefficient determining the his position in the group ntov). Block 10 generates a signal in the case when the code value at the outputs of block 2 is greater than the value at the outputs of switch 7. Thus, in the first cycle of operation at the second stage, block 0 does not emit a signal, and at the second

then with the same signal through the OR element 36, the counter 35 is nullified. The number n recorded in register 34 represents the number of elements of the first decomposition coefficient group and determines the further order of the order in the second stage.

At the second stage, the ordering of coefficients within the selected group is carried out almost similarly to the prototype device. The signal from the sixth output of block 5 permits the execution of the second stage of the ordering procedure, the operation of blocks 37 and 39, the supply of clock pulses from the generator 26 through AND 28 and OR 33 elements to the counter 35, the issuance of the corresponding codes from block 8 to block 10, switching of the second switch from the mode of connecting the first outputs with. output of block 5 to the connection mode

the outputs of the address register to the input of the block 35 37 comparison is a set of

ka 8 memory numbers of coefficients. Block 8 can be performed, for example (as in the prototype), in the form of a paired memory block, both halves of which are identical and contain the same values of the decomposition coefficients. One half at the second stage of the ordering gives out the address signal from the first outputs of block 5 the binary code of the current coefficient to the outputs of counter 3, and the other half - the code of the greatest ordering of the coefficient in the group at the outputs at the address determined by the state of the register 11 At the first time (the address register is in the zero state), at the first operation cycle of the counter 35, the identical codes of the first coefficient of the group recorded at the first address are received at the inputs of the second block 10 to distinguish the coefficient number detecting a position generally its array n coefficients, and

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matching circuits, the inputs of each of which are connected to the same outputs of the counter 35 and the register 34, are similarly implemented and the comparison element 39. Element 37 outputs a signal by which through element OR 36, counter 35 is set to the zero state. The contents of counter 38 are incremented by one. From the second 45 block 5, an enable signal is sent to the encoder 12 and the key block 13, through which the number of the maximum coefficient in the group through the encoder 12 is fed to the device 24 from block 9 and the value of this coefficient from block 8. The value of the maximum coefficient also goes through the key block 13 and the shaper 14 of the number module to the adder 15 and further to the block 16 of the comparison. The signal from the second output of block 5 also goes to block 8 and zeroes the contents of this block at the address of the maximum coefficient in order to exclude its fate from 50

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the second group coefficient and the first coefficient are compared to the cycle. With each tick of the counter 35, the address of the coefficient, which determines its position in the group of n elements). Block 10 generates a signal in the case when the code value at the outputs of block 2 is greater than the value at the outputs of switch 7. Thus, in the first cycle of operation at the second stage, block 0 does not emit a signal, and at the second

The coefficient of the inputs at block 2 is increased by one. In the absence of a signal from the outputs of block 10, the address recorded in register 11 remains unchanged, and when block 10 trips, which causes the current coefficient to exceed the value of the compared coefficient, the address of the current coefficient is written to the address register (corresponding to the state of the counter 35). Thus, by the end of the process of enumerating all the p coefficients of the group, the outputs of the switch 7 present the value of the largest coefficient in the group, the outputs of blocks 11 and 9 are its address,

and at the outputs of block 9 - his number.

When the comparison for all coefficients of the group is completed, the codes in the counter 35 and the register 34 are the same, which is fixed by the comparison block 37 (the element

0

matching circuits, the inputs of each of which are connected to the same outputs of the counter 35 and the register 34, are similarly implemented and the comparison element 39. Element 37 outputs a signal by which through element OR 36, counter 35 is set to the zero state. The contents of counter 38 are incremented by one. From the second 5 block 5, an enable signal is sent to the encoder 12 and the key block 13, through which the number of the maximum coefficient in the group through the encoder 12 is fed to the device 24 from block 9 and the value of this coefficient from block 8. The value of the maximum coefficient also goes through the key block 13 and the shaper 14 of the number module to the adder 15 and further to the block 16 of the comparison. The signal from the second output of block 5 also goes to block 8 and zeroes the contents of this block at the address of the maximum coefficient in order to exclude its fate from a distance

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within the group. The same signal is fed to the input of the divider 20, which can be implemented, for example, in the form of a counter and

intended for issuing a pulse at the output after the number of pulses corresponding to its division ratio is received at its input.

The signal from the second output, having passed through the OR element 45 from the seventh output of block 5, also wrapped the register of address 11.

Thus, as a result of the first comparison of the coefficients of the first group, the maximum coefficient in it is selected. The process then repeats. As a result of successive n / times of the second stage ordering process, all coefficients in decreasing order are transmitted to the recipient (with corresponding numbers) from the output of the encoder 12. For a complete ordering of the n coefficients, n,. p, n cycles of operation of the device. Counter 35 ensures that all coefficients are passed once and the maximum of the remaining ones is selected. Counter 38 provides n-times the passage of all coefficients for their full output to the recipient. After all the cycles have been completed, the contents of counter 38 coincide with the contents of register 34, with the result that the output of the comparison element 39 produces a signal that resets the counter 38 and increments the contents of the counter 41. The counter 41 determines the number of the code window whose value (window) is written by This address is in the memory block (17 or 18). Changing the contents of the counter 41 sets a new address in the memory blocks, and from one of them (working in this cycle of decomposition) a new value of the code window is fed to the first block 6 of code comparison. At the same time, the signal from the comparison element 39 through the third element OR 31 sets in one state the trigger 32. The device goes back to the first stage of ordering. From the clock pulse generator, the enable signal from the trigger 32 through the AND 27 element to the third output of block 5 and further through the OR 4 element to the counter 3 the clock pulses begin to flow and the elements are again searched

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array and sift them through a new, smaller in value in comparison with the previous code window. After selecting the second group of coefficients, the ordering of coefficients in it occurs, and so on.

Thus, in turn, the output of the device (encoder 12) receives the coefficient Q of the decomposition, ordered by magnitude. The end of the overall ordering cycle occurs in two cases. In the first case, the sum of the coefficients allocated to the adder 15, respectively. the required accuracy of the transform, o, ", p

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vania, set by the signal from bus 25 until the end of the enumeration of all elements of the array. At the same time, the output of the comparison block 16 to the second input of block 5 (on the OR element 44) receives a signal that brings the device back to its initial state (with the exception of the contents of memory blocks 17 and 18, which are installed only once at the 25 device start) . In the second case, after going through all the coefficients (elements of the array), the decoder 42 is triggered, at a signal from which the device also sets the JQ sec to the initial state. After this, the ordering process is repeated for a new array of coefficients.

Counters 35 and 38 have a capacity of n, guaranteeing an arbitrary number of coefficients in any group of the array of coefficients. The counter 44 has a capacity of N, corresponding to the number of code windows.

Consider the procedure for generating code window values, which is the main difference between the proposed device and the prototype. As previously indicated, during the initial installation of the device, some initial code window values are written into the memory blocks. One of the memory blocks issues a signal to the code comparison block 6 for implementing the coefficient ordering process in the given cycle. Which block does this, i.e. is working, it is determined by the signal from the trigger 21. If one of the memory blocks receives the signal 1 from the trigger, then the other - the signal O, which provides the readout mode from one of the blocks to the write mode to another memory block . Connecting one of the units (the one that is currently in o40

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readout) to block 6 is performed by the switch on the signal from the same trigger 21.

The main process of adjusting the device to the statistics of the decomposition coefficients is to write the corresponding values into the corresponding memory block. The optimal device performance is achieved by dividing the total array of coefficients into n pieces into N groups of n;

enta, where n j N -Jn.

code windows N, where N is -Jn, can be selected by knowing in advance the number of n. The values of code windows determining the number of decomposition elements falling into groups depend on the statistics of the distribution of the values of these coefficients and cannot be preselected. However, it is possible to make the current adjustment of the code window values for the statistics of the decomposition coefficients, which is realized in the proposed device.

For such an adjustment, a divisor 20 is used on the current cycle of transformation of the array of coefficients. Its division factor is -4p, i.e. a pulse is removed from its output when input pulses arrive at its input -fn. Its information input is connected to the second output of block 5, from which pulses come at the moments of response of the comparison element 37, i.e. at the moment when the ordering run occurred and the next factor in the ordered row is selected. Thus, the number of pulses applied to the input of the divider corresponds to the number of selected coefficients. When the N-th pulse arrives at the divider input, its sequence number is generally N |, where i 1, 2, 3 ... (the output signal from the divider allows writing to the corresponding memory block, to the one in this the loop is in recording mode, the value of the corresponding factor of decomposition from the second output of block 8). At the end of the conversion cycle in the memory block, the recorded n, coefficients (their values) with sequence numbers M (these coefficients serve as code windows in the next conversion cycle. In the next conversion cycle, this memory block is the source of

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other windows (this is provided by switching at the end of each conversion cycle of the trigger 21 with a signal from the fourth output of block 5), and another storage unit operates in the mode of recording new code window values for the next cycle. Thus, memory blocks 17 and 18 operate as sources of code windows alternately, changing in each conversion cycle.

With constant statistics of decomposition coefficients after the first conversion cycle due to the choice of the corresponding code window values, further cycles are performed with maximum speed, since all groups of coefficients contain n | coefficients. Some deviations in real cases from optimal performance occur due to the time variation of the statistics of the values of the decomposition coefficients, but since the coefficients from cycle to cycle correlate, these deviations are minor and are constantly worked out by writing to the memory blocks the current values of N- -X coefficients, which are used in subsequent cycles as code windows.

Thus, by constantly adjusting to the statistics of the set of decomposition coefficients, the proposed device allows for the performance-optimal transformation.

Claims (1)

... Invention Formula An adaptive telemetry device containing a coefficient input unit, the first inputs of which are information inputs of the device, the first and second outputs of the coefficient input unit are connected respectively to the first inputs of the buffer memory block and the first input of the OR element, the output of which is connected to the first input of the counter, The first outputs of which are connected to the first inputs of the memory of the addresses of the coefficients and the second inputs of the block of the buffer memory, the outputs of which are connected to the first inputs of the memory of the coefficient ntov first and bloka.sravneni codes, the first code comparing unit output is connected to the second 0 five 0 five inputs of the coefficient memory block and the coefficient address memory block by the third input of the buffer memory block and the first input of the program-time block, the first outputs of which are connected to the third inputs of the coefficient memory block and the first inputs of the address register, whose outputs are connected to the fourth memory inputs of the coefficient block, the first and second outputs of the coefficient memory block are connected respectively to the first inputs of the second code comparison block and the first inputs of the key block and the encoder and the second inputs of the second block Comparison of codes, the output of which is connected to the second input of the address register, the output of the memory of the coefficient addresses is connected to the second input of the encoder, the outputs of which are information outputs of the device, the second output of the program-time block is connected to the third input of the encoder, the fifth the input of the coefficient memory and the second input of the key block, the outputs of which are connected to the first inputs of the comparator through serially connected driver of the module and the adder, the second inputs of which are switched to the buses tolerance signals, the output of the comparison unit is connected to the second input of the software-time unit, the third input of which is the input of the initial installation, the third and fourth outputs of the software-time block are connected respectively to the second input of the OR element and the second input of the counter, the second output of which is connected to the fourth the input of the program-time block, fifth, ten 15 20 6352S6 4 The sixth and seventh outputs of which are connected respectively to the second input of the coefficient input unit, the sixth input of the coefficient memory input unit and the third input of the address register, characterized in that, in order to improve the speed of the device, switches, memory blocks, frequency divider are introduced into it trigger, inverse and direct outputs of which are connected respectively to the first input of the first RAM block and the first inputs of the second RAM block and the first switch, the outputs of which are connected with the second inputs of the first block of code comparison, the second and third inputs of the RAM block are respectively combined and connected to the input of the initial installation of the device and the second output of the coefficient memory block, the eighth outputs of the program-time block are connected to the fourth inputs of the first and second RAM blocks ti, the outputs of which are connected respectively to the second and third inputs of the first switch, the first, second and third inputs of the second switch are connected respectively to the sixth and first outputs the program-time block and the output of the address register, the first input of the frequency divider is connected to the second output of the program-time block, the second input of the frequency divider is combined with the trigger input and connected to the fourth output of the software-time block, the output of the frequency divider is connected to the fourth inputs of the operational memory blocks ti. 25 thirty 35 40 §five n fc VJ "V four S5f to about: LOS5 va I J