SU1327087A1 - Information input device - Google Patents

Abstract

The invention relates to automation and computing and can be used as a device for inputting output frequency values generated by a frequency synthesizer. The purpose of the invention is to expand the field of application by transforming information by multiplying and adding to a constant. The device comprises a keyboard I, a keyboard interface 2, a memory block 3, a control block 4, a pulse generator, a pulse distributor 5, a group of registers 7-10, registers II and 6, an adder 12, a CMM element 13 and an AND 14 element. The code of the digits of the frequency value, recorded in memory block 3, is read sequentially, starting with the lower digit. At the same time, the read code is converted by means of register 11 and adder I2. Data change at the output of the device is also performed sequentially by discharge when pressing the keyboard input. I zp f-ly., I table. e /)

Description

one

The invention relates to automation, computing and instrumentation and can be used as a device for inputting the output frequency values generated by a measurement generator.

The purpose of the invention is to expand the scope by transforming information by multiplying and adding with a constant.

In Fig. 1) a structural diagram of the proposed device is shown; Fig. 2 shows a schematic of the control unit; FIG. 3 shows an example of a block diagram of a memory unit.

The device (Fig. 1) contains a keyboard of 1 numbers and commands, a keyboard interface unit 2, a memory unit 3, a control unit 4, a distributor 5 pulses, a second register 6, a group of registers 7-10 (the major is a register 7, the total number registers - 10), the first register 11, the adder 12, the element 13 OR, the element 14 And, the inputs and outputs 15-22 elements of the device.

The control unit 4 (FIG. 2) contains a pulse generator 23, a decoder

1327087

Suppose that the operator sets the frequency of the output signal of the frequency synthesizer, which includes the proposed device.

The block 2 interface with the keyboard 1 generates a binary command code Setting the frequency, which is fed to the input 1Q of the decoder 24. The signal from the output of the decoder 24 to the 1-input of the trigger 25 ensures that it is set to state 1, as well as clears registers 35-37 of memory block 3 from 5 previously entered information.

The operator then dials the number of the frequency value, by successively pressing the keypad button,

In this case, the interface unit 2 generates a binary code of digits, which is fed to the data input of the memory unit 3. At the same time, the digit code is decrypted by detector 24 of the control unit 4 and co. the corresponding pulse is fed to the 25th input of the recording of the memory block 3.

As a result, the code of the output signal frequency Kp is fixed in memory block 3.

The binary-decimal code of digits often24, trigger 25, element 26 I, element AOR, fixed in block 3 of memory, 27 OR, counter 28, first 29 and second 30 elements NOT, register 31 moves to the input of the first register 11 sequences defined e-. my address code at the outputs of the 19th group of the control unit 4. The fixing of the code of each digit in register 11 occurs on the pulse front from the output 21 of control unit 4. Register 11, in conjunction with adder 12 and elements 14-I and 13, OR provides conversion of the frequency code K so that the data code at the output of the device Cd is related to the code Cd by the ratio

ha, counter 32 and a differentiating chain of capacitor 33 and resistor 34.

The memory unit 3 (FIG. 3) can be made in the form of a chain of successively connected four-bit registers 35-37, the outputs of which are switched using multiplexer 38

The device works as follows.

In the initial state, the pulses from the output of the generator 23 are fed to the input of the counter 28 (Fig. 2), and from its output to the input of the counter 32 of the address code operating in cyclic mode with a conversion factor equal to the number of registers 7-10 (the conversion factor in in this case it is equal to 10). The signals from the output of the counter 32 are fed to the address inputs of the memory block 3 by sequentially reading the code of the digits of the generator output signal, and to the inputs of

limiter 5 pulses, providing a sequential change of data at the output of the device in the presence of pulses from the output 22 of the control unit 4.

1327087

Suppose that the operator sets the frequency of the output signal of the frequency synthesizer, which includes the proposed device.

The block 2 interface with the keyboard 1 generates the binary command code Setting the frequency that enters the input of the decoder 24. The signal from the output of the decoder 24 to the 1-input of the trigger 25 ensures that it is set to state 1, and also clears registers 35-37 of block 3 of memory from previously entered information.

The operator then dials the number of the frequency value, by successively pressing the keypad button,

In this case, the conjugation block 2 generates the binary code of the digits arriving at the data input of the memory block 3. At the same time, the digit code is decrypted by detector 24 of the control unit 4 and co. The corresponding pulse is fed to the recording input of the memory block 3.

As a result, the code of the output signal frequency Kp is fixed in memory block 3.

Binary-decimal code of frequency digits, fixed in block 3 of memory

enters the input of the first register 11 in the sequence defined e-. my address code at the outputs of the 19th group of the control unit 4. The fixing of the code of each digit in register 11 occurs on the pulse front from the output 21 of control unit 4. Register 11, in conjunction with adder 12 and elements 14-I and 13, OR provides conversion of the frequency code K so that the data code at the output of the device Cd is related to the code Cd by the ratio

25-10.

Ka

5, Kf

+

gQ

g Such a Conversion is necessary to bring the code of the frequency to be set to the value of the division factor of the frequency divider included in the frequency synthesizer.

The conversion is performed sequentially, digit by digit by multiplying the number by 10, which is achieved by shifting the input number by one decimal place by overwriting it in register 12 and then dividing by 2 any i-th notebook of the input number, which is equivalent to simply shifting it to the right . In addition, the number 5 is continuously added to the ninth dec 55

ten

Full bit, and the number 2 is constantly recorded in the high order register register 7 group.

The conversion of the input data of the code of the set frequency Kg occurs continuously, however, no data is changed at the output of the device due to the lack of clock pulses at the output 22 of the control unit 4.

The data change at the output of the device occurs after the operator presses the button of the frequency measurement unit.

In this case, the binary command code from the block 2 of the conjugation enters the control block 4, decrypts and allows the clock pulses from the output of the shift register 31 to pass through the element 26 And to the synchronization inputs of the register group 7-10 and the second register 6. As a result, the outputs 17 of the device . there is a change of data. The order of the data change is determined by the address code at the input of the distributor 5.

As an illustration of the frequency code conversion process, an example of processing is given for the settable frequency f 1234567 x X 890 Hz (K 1234567890 value). The intermediate results of the code processing of the frequency value are summarized in a table (the initial cycle is given under the assumption that register 11 was previously cleared). I

As follows from the table and taking into account the connection of the second bit of the data input of the second register 6 to the signal 1, the data code - the output of the device corresponds to the number 31172839450, the 40th input of the first register, the output which is the sum, the OR element is connected to the first and

the third bits of the first group of inputs of the adder, the second group of inputs. Thus, the proposed device has a wider function of the outputs of the first register, the rational possibilities due to the output of the fourth bit of the second group of inputs the adder is connected to the bus, the information output of the first register is connected to the first information-CQ input of the second register, the second information input of which is tied by the input of the control unit, the group of outputs of the interface block common with the information inputs of the memory unit and the control unit, the first output of the control unit is connected to the synchronization input of the memory unit, the output group of the control unit is connected to the address inputs of the memory unit, the second output of the control unit is connected to the synchronization input of the first register, pulse distributor outputs connected to the control inputs of the group registers, whose outputs are the first group of device outputs, the third output of the control unit is connected to the synchronization inputs of the group registers, distinguishing with the fact that

20 expanding the field of application by transforming information by multiplying and adding with a constant, an element AND AND an OR element is entered into the device; a group of outputs of the control unit 25 is connected to the inputs of the pulse distributor, the first of the outputs of the pulse distributor is connected to the first inputs of the AND element and the OR element, the fourth output of the control unit

30 is connected to the reset input of the memory block, the group of information outputs of the memory block is connected to the group of information inputs of the first register, the information output of the memory block co2g is single with the second inputs of the AND element and the OR element, the output of the AND element is connected to the transfer input of the adder,. the second and fourth bits of the first group of inputs of the adder and the information maker for 5 values of the settable and constant - 25-10.

completeness when entering information multiplication and addition with a constant.

Claims (1)

Invention Formula - 1, A device for entering information containing a keyboardJ keyboard interface unit, a memory block that is connected to bus 1, a third and a fourth ABOUT information inputs to the bus and, the outputs of the second register are unidirectional, pulse distributor, 55 ° device output group, register group, two registers, summing control input of the second register mater, keyboard outputs are connected to the inputs of the interface with the keyboard connected to the last output of the pulse distributor, the synchronization input of the second register swarm whose output is connected to st0 0 one input of the first register, the output of the element OR is connected to the first and control module input, interface block output group is connected to the information inputs of the memory block and control block, first output of the control block is connected to the synchronization input of the memory block, output group of the control block is connected to the address inputs of the memory block, second output of the control block connected to the synchronization input of the first register, the outputs of the pulse distributor are connected to the control inputs of the registers of the group, whose outputs are the first group of outputs of the device, the third output of the control unit detecting synchronization inputs coupled to the group of registers, characterized in that, in order 0 expanding the field of application by transforming information by multiplying and adding with a constant, an element of AND is entered into the device, and the OR element; the group of outputs of the control unit is connected to the inputs of the pulse distributor, the first of the outputs of the pulse distributor is connected to the first inputs of the AND element and the OR element, the fourth output of the control unit 0 is connected to the reset input of the memory block, the group of information outputs of the memory block is connected to the group of information inputs of the first register, the information output of the memory block is connected to the second inputs of the AND element and the OR element, the output of the AND element is connected to the transfer input of the adder,. the second and fourth bits of the first group of inputs of the adder and informational to bus 1, the third and fourth ABOUT information inputs to the bus and, the outputs of the second register are connected to the last output of the pulse distributor, the synchronization input of the second register connected to the third control output. 2, The device according to claim 1, wherein the control unit comprises a decoder, a pulse generator, a trigger, an OR element, an AND element, two counters, and a shift register m, two. the NOT element, the gate input and information inputs of the decoder are respectively the gate input and information outputs of the block, the gate input of the decoder is connected to the reset inputs of the counters and the trigger synchronization input, the output of the first counter, the first output of which is connected to the input of the first element NOT, the output of which is connected to the clock input of the shift register, the output of which is connected to the first input of the element 0000 1001 1000 0111 it 0101 oyo UN 0010 0001 0000 0000 1000 .1000 it UN 0100 0100 0010 UN And AND, whose output is the third output of the block, the second output of the first counter is connected to the input of the second element NOT, the output of which is connected to the information input of the shift register, the counting input of the second counter and is the second output of the block, the outputs of the second counter are a group of high voltage blocks first exit the decoder is connected to the input of the installation in 1 trigger and the first input of the OR element, the output of which is the fourth output of the block, the second output of the decoder is connected to the input of the installation in O of the trigger and the second input of the OR element, the output of the trigger I, the third output the decoder is the first output of the block, the fourth output of the decoder is connected to the third input of the element I. 0000 0101 0100 1001 UN 1000 0010 0111 0001 0001 18 lHb 20 Editor E. Kopcha Compiled by I.A. Karnova, Tehred L. Serdyukova Proofreader V. But ha Order 3390/45 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 FI.2 (pus.3