SU934470A1 - Device for dividing numbers represented in pulse-number code - Google Patents

Description

(54) DEVICE FOR DIVIDING NUMBERS

SUBMITTED BY PULSE The invention relates to automation and computer technology and is intended for information measuring and processing systems. A device is known comprising a driver device connected through a control valve circuit with counters, a detector valve and forming cxeNbi, one of the inputs of the control valve circuit being connected to an input source, and the second to the detector output, one short-circuit output control valve circuit is connected to the counter input, and the second - with valve circuits. The disadvantage of this device is low division accuracy for a given speed, because the number-pulse code of the layout can be shared only with to the whole, i.e. the divisor can take only integer values. The closest to the present invention is a device containing N CODES of decade reversible counters (where N is 1,2, .., n, n is the number of bits of the dividers l), divider task blocks, first element I, pulse generator, result counter the first input of the pulse generator is connected to the input bus of the device, the output of the pulse generator is connected to the first input of the first element I, the outputs of the divider assignment blocks are connected to the inputs of the summation of N decade reversible counters, the output of the nth decade reversible counter a counter input result f2}. A disadvantage of the known device is low speed with a given accuracy of division. This is because the frequency of the master oscillator is 10 times higher than the frequency of the input number-pulse code. For a given high divisional accuracy, in order to perform such a relationship, it is necessary to impose a limit of 39 on the maximum pulse frequency of the input number-pulse code. The purpose of the invention is to increase the speed of the device for a given division accuracy. The goal is achieved by the fact that a shift register is entered into the device, M are decade reversible counters {where M n + 1, n + 2, ..., 2 n), the second and third elements AND, five elements OR, and the installation input The shift register is connected to the input of the result counter and with the combined summation inputs M of decade reversible counters, the output of the first IL element is connected to the information input of the shift register, the first output of which is connected to the second input of the first element I, the output of which is connected to the subtraction entrances n and the first- (n + 1) -th decadal reversible counter, the second output of the shift register is connected to a first input of the second AND gate, the second input of which cos

dinene with the first input of the first element AND and the first input of the third element AND, the output of which is connected to the first inputs of the second and third elements OR, and the second input to the third output of the shift register, the output of the second element AND connected to the first inputs of the fourth and fifth elements OR the second input of the fourth element OR is connected to the output of the (n + 1) -th decade reversible counter, and the output is subtracted by the input of the (n + 2) -th ten-day reversible counter, the output of which is connected to the second input of the second CM element, the output of the first ten-dayreversible counter is connected to the first input of the first element OR and the second input of the fifth element OR whose output is connected to the subtractive input of the second decade reversible counter, the output of the last is connected to the second inputs of the first and third elements OR, the output of the second element OR is connected to the subtractive input 2n-th decadal reversible counter, the summation input of which is connected to the input bus of the device, the output of the 2nth decade reversible counter is connected to the second input of the pulse generator, the output of the third el OR is connected to the subtracting input of the nth decade reversing counter.

The summation inputs of the decade reverse meters 4-6, the output of element 14 OR are connected to the information input of the 18-shift register,

the first output of which is connected to the second input of the element 17 I, the output of which is connected to the input inputs of the decade reverse meters 1 and 4, the second output of the shift register 18 is connected to the first input of the element

15 And, the second input of which is connected to the first input of element 17 And and the first input of element 16 And, the output of which is connected to the first inputs of elements P and 13 Sh1I, and the second input to the third output of shift register 18, the output of element 15 And connected to the first inputs of elements 10 and 12 OR, the second input of the element 10 OR connect) with the output of the ten-day reverse

counter I, and the output with the subtracting input of the ten-day reversible counter 2, the output of which is connected to the second input of the element 1I Ш1И, the output of the ten-day reversible counter 4

connected to the first input element 14 OR and the second input element 12 ShI, the output of which is connected to the subtractive input of the ten-day reversible counter 5, the output of which

Claims (2)

connected to the second inputs of elements 13 and 14 OR, the output of element 11 OR is connected to the subtracting input of a ten-day reversible counter 3, input The drawing shows the functional diagram of the proposed device for dividing the numbers represented by the number-pulse code. The device contains decadal reversible counters 1-6, blocks 7-9 of setting the divider, elements 10-14 OR, elements 15-17 AND, shift register 18, start-stop pulse generator 19, input bus 20, result counter 21. In the device, the first input of the start-stop generator J9 of pulses is connected to the input bus 20 of the device, the output of the start-stop generator of 19 pulses is connected to the first input of element 17 I, the outputs of blocks 7–9 of setting the splitter are connected to the summation inputs of decadal reversible counters 4 -6, the output of the decade reversible counter 6 is connected to the input of the result counter 21, the setup input to the initial state of the shift register 18 is connected to the input of the result counter 21 and from the summation of which is connected to the input bus 20 The output of the ten-day reversible counter 3 is connected to the second input of the start-up generator of 19 pulses, the output of element 13 of the pin is connected to the read input of the ten-day reversible counter 6. The device operates as follows. At the command Initial installation (buses of this command are not shown 1 ) counter 1-3 are zeroed, a stop signal is given to the start / stop generator 19 (pulse generation prohibition), into counters 4-6 are entered with a parallel digit code from setting blocks of divider 7–9, respectively, the first digit of shift register 18 is set is 1, the other bits of this register are set to ON, the counter 21 is zeroed result. In blocks of setting divider 7–9, the value of divider is preliminarily typed, and the drawing shows three consecutive digits of the dial of divider, the start bit is dialed in block 9, and the low order is dialed in block 7, For example, the number 13 is dialed like this. In block 9, the digit O is set, in block 8, the digit 1, in block 7, the digit 3, The removal of the Initial Setup command is the moment the device starts operating. The input bus 20 begins to receive pulses of a number-pulse code, which must be divided by the number dialed in the blocks of the divider task 7–9. Let, for example, the code received on the input bus 20, be divided by the number 1, 3. Below, the operation of the device is shown in this example. So, in the task setting block, divider 9 is set to O, in block 8 - digit 1, and in block 7 - digit 3, After the end of the Initial installation command, the code 4 is recorded in the counter 4, the number 1 in the counter 5, in the counter 6 O is written to the input bus 20, the first pulse is sent through this pulse to the counter 3 is recorded 1, since the input bus 20 is connected with the summing up of the input of the counter 3. This pulse also goes to the starting input of the start generator 19, at the output which are formed by high frequency pulses KOVI, acting on the input of the element 17 And, at another input which o06 potential of allowing the first output 18 of the shift register. Note that elements 15 and 16 And the start-stop generator 19 pulses cannot pass, because at this moment the second and third outputs of the shift register 18 are prohibiting, the potential is zero From the output of element 17 And the high frequency pulses go to the subtracting inputs (X) 1x reversible counters 1 and 4. The first impulse from the output of element 17 And subtracts one from the number in counter 4, i.e. in counter 4, the code of the number two remains. Counter 1 is zero, therefore subtracting a unit from counter 1 triggers a Loan signal at its output, while code 1 remains in Counter 1, and the Loan Signal at the output of counter 1 through element 10 OR goes to subtract the input of counter 2, since counter 2 also set to zero, the Loan signal is generated at its output, and the code 2 remains in Counter 2, the Loan Signal from the output of counter 2 through element 11 OR goes to the subtracting input of counter 3, the caNftiiM subtracts the unit that was recorded in this counter in counter 3 code zero remains. The second pulse from the output of element 17 also subtracts one from the numbers in counters I and 4, the number 1 remains in counter 1, and the number 1 remains in counter 4, and the third pulse from the output of element 17 leaves number I in the counter I, and the counter 4 is zeroed out, while the leading edge of the Loan signal from the output of counter 4 through the element 14 OR goes to the clock input of the shift register 18, that 1 from the first bit of this register is shifted to the second bit. In the first bit of the de 18 register the shift remains zero potential that prevents the passage of pulses through ement 7, and since the second bit of the shift register 18 is coupled to an input of AND element 15, the fourth pulse start-stop oscillator 19, passes through element 15 and (the resolution is the second discharge register 18 shift). This pulse comes from the output of element 15 AND through element 10 OR to the read input of counter 2 (in code 2 the result is the code of number 8) and through item 12 OR to the read input of counter 5, the counter 5 is zeroed and the leading edge of the signal is Loan from the output of this counter 5 through the element 14 OR in the shift register 18 is shifted to the third bit (from the second) 1, while the resolution on the passage of the pulses of the stationary generator 19 is applied to the element 16 AND, However, since the output of the counter 5 Signal loan, and the front of this si The sensor enters through the element 13 OR at the readout input of the counter 6, and this counter 6 is reset, and the leading edge of the signal is formed at the output of the counter 6 Loan, by this signal the shift register 18 is set to the initial state (1 in the first discharge, in the remaining bits are 0). The same signal in counters 4-6 again sets the code from the blocks for setting the splitter 7-9, respectively, i.e. in counter 4, the code of the number 3; in counter 5, the code of the number 1; in counter 6, the code is zero. In addition, according to this signal from W) 1 of the counter 6, the result counter 21 records from one. The first division cycle is completed. Let's write numbers in counters 1-3 after the end of the first cycle. Counter Number 17 28 3О The second division cycle and the next one proceed similarly to the first cycle. We will show the numbers in the counters 1-3 and in the counter 21 of the result 1 after each division cycle. Second Cycle Third, Cycle Counters Number Counters Number 141i 272 6 3030 212213 Seventh Cycle Counters Number 1. 9 2О 3О 217 The eighth cycle begins analogs but the first cycle, i.e. in the counter the number 3, in the counter 5 - the number 1, in the counter 6 - zero. The first bit of shift register 18 is 1, 3 pulses are subtracted from counter 1, and from count 4, counter 4 is zeroed out, I is shifted to the second bit of shift register 18. However, since the counters 2 and 3 are set to zero, a Loan signal is generated from the output of the counter 3, which is fed to the stop input of the start-stop generator 19 and stops this generator. The generation of pulses is stopped, so nothing changes in the device until the second pulse arrives on the input bus 20, which writes 1 to counter 3, starts the start-stop generator 19, and so on. The result of the division after the first pulse on the input bus 20 is obtained in the counter 21. result, where the number 7 is written. Indeed, 1: 1,, 7. When the result is displayed in the counter 21, the result of the lower decade for this embodiment of the device is separated by a comma. The drawing shows only three bits to set the division factor, however, the number of these bits can be increased to the required. Thus, increasing the speed of the proposed device with a given division accuracy as compared with the known one is increased several times, and with a high given accuracy — by several orders of magnitude. . For the example given in the description (division by 1 C) in a known device Cleanliness of the pulse generator in the multiplier is 100 times higher than the frequency of the pulses of the input number-pulse code (for a given division accuracy). In this device, it is enough that the frequency of the pulse generator was at the same time as the frequency of the pulses of the input number-pulse code (in this case it provides the division by the maximum division factor for this particular mass –1.9.9), i.e. The speed and the performance of this device is 5 times higher than the known. If necessary, the division accuracy and the division ratio increase by including additional elements in the composition of the proposed device. At the same time, the speed increases in. times compared with the known. DETAILED DESCRIPTION OF THE INVENTION A device for dividing numbers represented by a number-impulse code. a house containing N decade reversible counters (. where N |, 2, ..., nj ti is the number of digits of the divider), blocks for setting the divider, the first And element, the pulse generator, the result counter, the first input of the pulse generator connected to the input bus of the device, the output of the pulse generator is connected to the first input of the first element I, the outputs of the divider task blocks are connected to the inputs of the summation of N decade reversing counters, the output of the nth decade reversible counter is connected to the input of the result counter, what with The purpose of improving the speed of the device for a given division accuracy is that a shift register, M decadal reversible counters (where, n-fZ ,, .., 2п), second and third elements AND, five OR elements are entered into it, and the installation input is initial the shift register is connected to the input of the result counter and combined with the {9 1 input of the summation f of the ten-day reversible counters, the output of the first element OR is connected to the information input of the shift register, the first output of which is connected to the second input of the first element AND whose output n with reading inputs of the first and (n + 1) -th decade reversible counters, the second shift register output is connected to the first input of the second element and whose second input is connected to the first input of the first element And and the first input of the third element And whose output is connected with the first inputs of the second and third elements OR, and the second input with the third output of the shift register, the output of the second element I is connected to the first inputs of the fourth and fifth elements OR, the second input of the fourth element ISH1 is connected to the output of (ti +1) -th decade reverse the output counter with the subtractive input of the (n + 2) -th decade reversing counter, the output of which is connected to the second input of the second OR element, the output of the first ten-day reversible counter is connected to the first input of the first OR element, and the second input of the fifth OR element, the output of which is connected to nlchitayu-. the second input of the second decade reversible counter, the output of the last one is connected to the second inputs of the first and third elements OR, the input of the second element OR is connected to the subtractive input of the 2nth decade reversible counter, the summation input of which is connected to the input bus of the device, the output of the ten-day reversible counter is connected with the second input of the pulse generator, the output of the third element OR is connected with the subtraction} the av91m input of the nth decade reversible counter. Sources of information taken into account during the examination 1. USSR author's certificate No. 311268, cl. q 06 F 7/52, 1969. 2. The author's certificate of the USSR 1 493924, cl. H 03 K 23/24, 1973 (prototype).