SU660231A1 - Converter of the ratio of two frequencies into code - Google Patents

Description

AND, the output of the trigger is connected through the delay element to the second input of the third logical element AND directly to the first input of the fourth logical element AND, the output of the third logical element AND to the control input of the block of logical elements AND, and the output of the fourth logical element AND the first control input of the controlled frequency divider, additionally introduced a counter, switch, subtraction unit, register, and period allocation unit. The input of the period allocation unit is connected to the bus of the second input signal, the first output is connected to the second input of the first logical element AND, and the second output to the second control input of the controlled frequency divider and the second input of the second logical element I. At the same time, one register input is connected to the output of the controlled frequency divider and one input of the subtractor, the second input of which is connected to the trigger input, and the output of the subtraction unit is connected to the input of the additional counter, the output connected to the control input to of the switch, the information inputs of which are connected to the buses of the reference frequency and its harmonics, and the output is connected to the second input of the fourth logical element I, the second input of the register is connected to the output of the third logical element I.

The structural electrical circuit of the described converter is shown in the drawing.

The converter contains a controlled frequency divider 1, counters 2, 3, AND block 4, register 5, AND 6-9 logic elements, switch 10, subtraction block 11, trigger 12, delay element 13, period selection block 14.

Input signals are fed to the input buses 15, 16, and the reference frequency and its harmonics are fed to the buses 17, 18, 19.

The output code is removed from exit 20.

The principle of operation of the device is as follows.

Device dependency modulation is

.TO

LA -.

where Mg is the output binary code; FX, Py - input frequencies;

n is the discharge current L is real in the device, instead of dividing FX, by Fy, their rhodes are divided, i.e.

l ..

Where

Tu /.ru - the period of the frequency Ru-, Tx I / FX - the period of the frequency FX.

For normal operation, the condition must be met.

 max - l MIN

In the operation of the device, two stages can be distinguished: the conversion of the period Tu to the binary code NT; division of Tu by Tx, as a result of which the output code LGB of the initial state determines the counters 2, 3 and the controlled frequency divider 1 is set to "O, and register 5 is written" 1 to the second bit. Coding the period Tu is done by filling it a high reference frequency FO using a period allocation block TU 14, an AND 8 logic element and a counter 2. A period selection block, which is based on a two-digit summing counter (not shown), operates in such a way that its first output has a high potential goes on the time interval between the first and second pulses of the frequency Py (i.e., during the frequency period), and at its second output after the end of the first period of the same frequency. Therefore, with the arrival of the first frequency pulse Fy, the logical element AND 8 is opened, and the counter 2 accumulates the code Lsc, 1 proportional to the period Tu, from O to magnitude. T.F ,.

With the arrival of the second frequency pulse, Py, the AND 8 closes, stopping the flow of the FO frequency pulses to the counter 2. This completes the encoding process for the period Tu.

Then the second stage begins: dividing TU by TX- The second pulse of the frequency Ru, causing the appearance of a high potential at the second output of the period extracting unit 14, rewrites the code N Tu from counter 2 to the controlled frequency divider 1 and, in addition, opens a logical element And 9.

The division process consists of repeating the same steps: subtracting from the dividend divider and doubling the resulting balance.

In the proposed device, the division is implemented as follows.

The first (after opening the AND 9 logic element) the PX frequency pulse sets trigger 12 to "1. In this case, the reference frequency Po from the switch 10 through the logical element 6 begins to flow to the counting input of the controlled frequency divider 1, writing off its contents from jVr to “O.” By the time of arrival of the next (second) pulse of the PX frequency, the contents of the controlled divider I of the frequency Mu h, decreases by the value of RoTx and becomes equal to

. -, - T ,, F, ::. F, (G, - G,), where, is the code of the residue AT Tu - Tx after the first step of dividing.

The second pulse of the FX frequency, passed the logical element AND 7, opens the block 4 of the logical elements AND, through which the code / ULG, is rewritten into counter 2. In addition, the same impulse is written to the low-order bit of register 5. So, in the first step of dividing the subtraction from the divisible Tu divider T is implemented and the ATi residue is obtained. Since the dividend turned out to be greater than the divisor, the highest digit of the private value is “1. Next, the Tx should be subtracted from the doubled first 2AG1 residue. It is done like this. After transferring the residual code, from the controlled frequency divider 1 to counter 2, the Ludch code continues to be described by the FO frequency impulses of the value, to zero. At the moment of zeroing, the input code is rewritten into it. In this device, the input is the code stored in counter 2. As the code is stored in counter 2 for this period of time, it is copied to the controlled frequency divider 1, and the process of decreasing its content () from N t is repeated. to zero The third pulse of the FX frequency, which arrived at this time interval, as well as its second pulse, makes a census from the controlled divider

I frequency counter 2 of the next (second) balance equal

N, T, 2N, T.-T ,.

The third pulse of the FX frequency, as well as the second pulse, records "1 for the first bit of register 5. Previously recorded" 1 by this time is already shifted to the second bit of register 5 by means of the output frequency pulse () formed at the moment of zeroing of the controlled divider frequencies. In the two division steps considered, the dividend (Tu and 2ATi) is greater than the dividers 7. Therefore, at each step, the next private digit is assigned the value 1 and the private code is shifted to the left. The example is chosen so that the doubled second residue is less than the divisor, i.e.

2DG, G ,.

Therefore, after the second zeroing of the controlled frequency divider in the third period, the FX frequency (i.e., after the two additional pulses ud) that came at the output of the block

An I1 pulse emerges, which is recorded in counter 3. From the switch 10, the frequency Fo / 2 arrives, and therefore the next impulse frequency ud appears LG2

with a time equal to,

0/2 i.e. 2A72. Since in this example

DG, + AG, + 2LG, G „

then the output of block 11 is another impulse, which, by changing

the code in the counter 3, switches the switch to the issuance of the frequency Foi2.

In accordance with this, the next period of frequency / - of the output will be twice as large

the previous one. If now DG2 + AG2 -f + 2A72 + 4AG2 TX, then the process will be repeated. Otherwise, as in this example, the situation is repeated, similar to the first two divisions.

The proposed device allows, due to a slight complication of the circuit, at the same time as the division operation, to convert the frequency into a code. Using it as a device

pairing frequency sensors in a digital computer makes it possible to unload the latter from the most laborious division operation for it.

Claims (2)

Invention Formula A converter of the ratio of two frequencies into a code containing a controlled frequency divider, the bits of which are connected to the outputs of the bits of the counter, the outputs The bits of the controlled frequency divider are connected to the inputs of the AND block, the outputs of which are connected to the inputs of the counter bits, the information input of which is connected to the output of the first AND logic gate, one input of which is connected to the reference frequency bus, the second logic element AND, one input of which is connected to the slit of the first input signal, and the output of the second logic element I is connected to the input of the trigger and the first input of the third logic element I, the output of the trigger is connected through the delay element with sec The input of the third logical element is And directly with the first input of the fourth logical element And, with the output of the third logical element And connected to the control input of the block of logical elements And, and the output of the fourth logical element And connected to the first control input of the controlled frequency divider, that, in order to increase accuracy, a counter, switch, subtractor, register are additionally introduced into it and a period selection unit, the input of which is connected to the bus of the second input signal, the first output of the period selection unit is connected to the second input of the first logical element AND, and the second output of the period allocation unit is connected to the second control input of the controlled frequency divider and the second input of the second logical element And, at the same time, one register input is connected to the output of a controlled frequency divider and one input of the subtracting unit, the second input of which is connected to the trigger input, and the output of the subtracting unit is connected to the additional input an output counter, the output of which is connected to the control input of the switch, the information inputs of which are connected to the reference frequency buses and its harmonics, and the output of the switch is connected to the second input of the fourth logical element AND, the second input of the register is connected to the output of the third logical element I. Sources of information , taken into account during the examination 1. For the UK N ° 1365761, cl. G 4H, pub. 1974. 2. For the name of Janonia No. 43-30332, cl. Do, publish. 1968.