JP2538095B2 - Synchronous protection circuit - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problem Action Example Effect of the invention [Summary] Various synchronization patterns A synchronous protection circuit capable of supporting one or a plurality of devices, for the purpose of arbitrarily setting a synchronous pattern and the number of protection stages, a synchronous bit extracting means for extracting a synchronous bit in input data, and a predetermined number for each address. A random access memory that stores a part of the pattern and the address of itself that stores the next part of the predetermined pattern; a predetermined pattern included in the data read from the random access memory; The extracted synchronization bit and the comparison means for detecting the coincidence of these are inputted, and when the coincidence is detected by the comparison means, random comparison is performed. The address setting means that selects its own address included in the data read from the access memory and inputs the selected address to the random access memory when a mismatch is detected, and the data read from the random access memory are specified. And a synchronization detecting means for detecting out-of-synchronization at other times.

[Industrial applications]

The present invention relates to a sync protection circuit that can be applied to one or a plurality of devices having various sync patterns.

In the reception synchronization control unit of a digital communication device, a technique is generally used in which a specific pattern is inserted in one frame on the transmitting side in order to establish frame synchronization, and the receiving side detects this pattern to identify the frame. There is. The synchronization protection circuit is used in such a reception synchronization control unit to avoid error synchronization and maintain a normal synchronization state.

In recent years, with the development of the information industry, the number of devices connected to many networks has increased, and since the synchronization protection circuit must also correspond to each synchronization pattern, it is necessary to share the circuits and provide versatility. is there.

[Conventional technology]

A general synchronization protection circuit compares a 1-bit or multi-bit synchronization pattern extracted from data with a specific pattern and a pattern comparison circuit that holds the comparison result for the number of protection stages to detect out-of-sync or synchronization establishment. It is configured with front and rear protection circuits. Here, the pattern comparison circuit is realized by a combination of a decoder or a shift register and a logic gate, and the front and rear protection circuits are realized by a combination of a counter or a shift register and a logic gate.

For example, when the pattern comparison circuit is realized by using a decoder, a predetermined number of input synchronization bits are held, and the held plural bits of data are input to the decoder. Therefore, pattern comparison can be performed by using a decoder that outputs a coincidence signal when the input data has a specific pattern. Also, when the front and rear protection circuits are implemented by using a counter, the coincidence signals or non-coincidence signals that are continuously output are counted by the counter, and when a predetermined count value is reached, synchronization is established or out of synchronization is detected. I do.

[Problems to be Solved by the Invention]

By the way, in the above-mentioned conventional method, since the synchronization protection circuit is configured by hardware, there is a problem that the specific pattern and the number of protection stages to be compared are fixed. Therefore, if the synchronization detection is performed for several types of synchronization patterns or the number of protection stages, the above-mentioned synchronization protection circuit must be prepared according to the types of the synchronization patterns or the number of protection stages, resulting in an increase in circuit scale.

As a conventional technique for reducing the circuit scale by changing the number of protection stages, there is a synchronization protection circuit disclosed in Japanese Patent Laid-Open No. 61-276435. This synchronization protection circuit freely sets the number of protection stages by determining the timing of resetting the counter by the counter reset circuit.
Only by making both the synchronization pattern and the number of protection stages variable, synchronization detection for an arbitrary communication destination is realized, and a synchronization protection circuit capable of arbitrarily setting both of them has been desired.

Further, as a conventional technique in which the synchronization pattern and the number of protection stages can be easily changed, there is a frame synchronization circuit disclosed in JP-A-61-139140. Since this frame synchronization circuit uses a programmable read-only memory to set the synchronization pattern and the number of protection stages, it has the advantage of being able to easily respond to design changes, etc., but is connected to multiple communication destinations and may be connected as necessary. If the combination of the synchronization pattern and the number of protection steps is changed each time, it cannot be dealt with. Therefore, there has been a demand for a synchronization protection circuit capable of appropriately switching the settings of a plurality of synchronization patterns and the number of protection stages.

The present invention was created in view of such a point, and an object thereof is to provide a synchronization detection circuit capable of arbitrarily setting a synchronization pattern and the number of protection stages.

[Means for solving the problem]

FIG. 1 is a block diagram of the principle of the synchronization protection circuit of the present invention.

In the figure, a sync bit extraction means 111 extracts a sync bit in the input data.

The random access memory 121 stores a part of a predetermined pattern at each address and its own address in which the next part of the predetermined pattern is stored.

The comparison unit 131 receives the predetermined pattern included in the data read from the random access memory 121 and the synchronization bit extracted by the synchronization bit extraction unit 111, and performs matching detection of these.

The address setting means 141 selects its own address included in the data read from the random access memory 121 when the comparison means 131 detects a match, and selects a predetermined address when a mismatch is detected. The random access memory 121.

The synchronization detecting means 151 detects the establishment of synchronization when the data read from the random access memory 121 reaches a predetermined value, and detects the loss of synchronization at other times.

Therefore, as a whole, the specific pattern stored in the random access memory 121 is sequentially read out and compared with the extracted synchronization bit to perform synchronization detection.

[Work]

Each storage area of the random access memory 121 stores a part of a predetermined pattern necessary for synchronization detection and its own address to be accessed next. Therefore, by inputting the address read together with the predetermined pattern into the random access memory 121 itself via the address setting means 141, it is possible to sequentially read the predetermined patterns. The comparison unit 131 compares the read predetermined pattern with the synchronization bit extracted by the synchronization bit extraction unit 111, and as long as the matching state continues, the above-described reading of data from the random access memory 121 continues. Then, when this read data reaches a predetermined value, the synchronization detection means 151 detects the establishment of synchronization.

Further, when the comparing unit 131 detects a non-coincidence state during the above-described synchronization detecting operation, the address setting unit 141 selects a predetermined address, and therefore the synchronization detecting operation is repeated by returning to this address.

In the present invention, the specific pattern stored in the random access memory 121 is sequentially read, and the synchronization detection is performed by comparing with the extracted synchronization bit. The synchronization pattern and the number of protection stages can be arbitrarily changed by making appropriate changes.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the structure of a synchronization protection circuit according to an embodiment of the present invention.

In the figure, reference numeral 211 denotes a sync bit extraction circuit,
1 is a random access memory (RAM), 231 and 235 are selectors, 233 is an exclusive OR gate, 241 and 245 are buffers, 243 is a flip-flop (FF), 261 is a match detection circuit, 271 Indicates a pulse generation circuit (PG).

The synchronous bit extracting means 111 shown in FIG.
The comparing means 131 corresponds to the exclusive OR gate 233, the address setting means 141 corresponds to the selectors 231 and 235, and the synchronization detecting means 151 corresponds to the coincidence detecting circuit 261.

The sync bit extraction circuit 211 is for extracting sync bits from the input data.

The RAM 221 is for storing a specific pattern for synchronization detection, and each bit of the specific pattern is stored together with the storage address of the next bit. That is, when a certain data is read, one bit of the data is used as one bit of the specific pattern, and the data excluding the one bit is used as an address for reading the next one bit of the specific pattern. ing.

The selector 231 is for selecting an address to be input to the address terminals A0 to A6 of the RAM 221, and when rewriting the contents of the RAM 221, a central processing unit (CPU, not shown)
Select the address from, and otherwise select the output of the selector 235.

The exclusive OR gate 233 is for comparing the synchronization bit extracted by the above-mentioned synchronization bit extraction circuit 211 with one bit of a specific pattern read from the RAM 221, and obtaining an exclusive OR output of these. . That is, if the extracted synchronization bit and the read specific pattern are equal, a logical "0" is output.

The selector 235 performs a selection operation according to the output logic of the exclusive OR gate 233. When the output logic of the exclusive OR gate 233 is “0” (when the synchronization bit and the specific pattern are equal), the output of the RAM 251 is selected, and when the output logic is “1”, a predetermined fixed data is selected. To do.

The buffer 241 is C when rewriting the contents of the RAM 221.
It is for inputting the data output from the PU to the data terminals D0 to D7 of the RAM 221, and otherwise sets its own output terminal to the high impedance state to disconnect it from the CPU side.

The flip-flop 243 is for taking in and holding the data output from the RAM 221, and the held content is input to the data terminals D0 to D7 of the RAM 251 via the buffer 245.

The coincidence detection circuit 261 is for detecting synchronization establishment and loss of synchronization based on the output of the RAM 221 held in the flip-flop 243, and the above-mentioned synchronization depending on whether or not the output content of the RAM 221 is equal to a predetermined pattern. Detect.

The pulse generation circuit 271 generates various control signals for giving an operation instruction to the above-mentioned components. Specifically, the frame clock FCLK is set to the synchronization bit extraction circuit 211.
In addition, a select signal * SEL (denoted by adding a * to a negative logic signal) is applied to the selector 231 and the buffer 241, a write enable signal * FRWE is applied to the RAM 221, and a latch clock *.
LCK to flip-flop 243, write enable signal *
The MFWE is input to the buffer 245 and the RAM 251 respectively.

 Next, the operation of the above-described embodiment of the present invention will be described.

FIG. 3 shows the operation timing of one embodiment. Less than,
The operation of the embodiment will be described with reference to FIGS. 2 and 3.

The synchronization bit extraction circuit 211 is configured to input each frame a,
From the data of b, ...
It is extracted at the timing when the frame clock FCLK rises (FIGS. 3 (a), (b), (c)).

In addition, the frame number corresponding to each frame data is RA
An address is input to M251 (FIG. 3 (d)), and 8-bit data including a specific pattern for comparison with the extracted sync bit is read. Here, the most significant bit of the 8-bit data corresponds to the specific pattern, and the other 7 bits correspond to the address of the RAM 221 in which the next specific pattern of the frame of interest is stored. Only the most significant bit of the data read from the RAM 251 is input to the input terminal of the exclusive OR gate 233, and if this most significant bit matches the extracted synchronization bit, the other 7 bits Is input as an address to the RAM 221 via the selectors 235 and 231.

Next, the RAM 221 outputs the data designated by the address input via the selector 231, that is, the next synchronization pattern of the frame of interest and the address of the RAM 221 itself in which the next synchronization pattern is stored. The flip-flop 243 fetches and holds this output data in synchronization with the falling edge of the latch clock * LCK output from the pulse generation circuit 271 (FIG. 3 (e)). The held data is stored in synchronization with the fall of the write enable signal * MFWE, and the data corresponding to the frame of interest is updated (Fig. 3 (f),
(G)).

In the example shown in FIG. 3, first, a specific synchronization pattern (1 bit) and the address NM of the RAM 221 (where N corresponds to the upper bits and M corresponds to the lower bits) are read from the RAM 251. The specific synchronization pattern stored at the address NM and the address N (M + 1) are read out from the RAM 221 and further stored in the RAM 251. In this way, when focusing on a certain frame, the lower-order address M is sequentially changed to M
By updating to + L, a synchronization protection circuit having the number of protection stages L is realized, and the coincidence detection circuit 261 detects that the address on the lower side has become M + L and establishes synchronization.

Further, when out-of-sync occurs and the extracted sync bit and the predetermined pattern do not match, fixed data is selected by the selector 235, and thus the above-described sync detection operation of the protection stage number L is repeated from the beginning.

By the way, the above-mentioned read data from the RAM 221 needs to be fixed when the data is taken into the flip-flop 243. Therefore, it is possible to write new data to the RAM 221 and change the stored contents at timings other than the above. The write enable signal * FRWE and the select signal * SEL output from the pulse generation circuit 271 are signals for controlling this write operation (FIGS. 3 (h) and (i)). When the logic of the select signal * SEL becomes "0", the data and address from the CPU are input to the RAM 221 via the buffer 241 and the selector 231, and then the RAM 221 is generated at the timing when the write enable signal * FRWE falls.
Data is written to the.

FIG. 4 shows a flow of operations up to establishment of synchronization when attention is paid to an address read from the RAM 221. The 2-digit number shown in the figure represents the 7-bit data excluding the most significant bit of the 8-bit data stored in the RAM 221, and the upper digit indicating the frame number is the upper 3 bits,
The lower digits indicating the number of synchronization stages correspond to the lower 4 bits, respectively.

When the sync bit and the specific pattern do not match, the output logic of the exclusive OR gate 233 is "1", so the fixed data "00" (all 7 bits are "0") are selected by the selector 235. , This fixed data is the address RA
Input to M221. In the area of the address "00" of the RAM 221, the first 1 bit of the specific pattern and the next 1 of the specific pattern
The address "01" where the bit is stored is stored,
This data read is repeated until the sync bit to be extracted matches the first bit of the specific pattern.

When the sync bit equal to the first bit of the specific pattern is extracted, the address is sequentially updated based on the data stored in the RAM 221. One horizontal row shown in FIG. 4 shows one protection step corresponding to one multi-frame, and the synchronization is established only when the final row is reached. After that, the last column is circulated until the synchronization is lost, and when the synchronization is lost, the initial address “00” is returned to and the synchronization detection processing is repeated.

In this way, the specific pattern is stored in a part of the data read from the RAM 221, and the address of the RAM 221 itself storing the specific pattern to be read next is stored in the remaining part. Therefore, the synchronization can be established by sequentially reading the specific pattern based on this storage address. Further, by controlling the buffer 241 and the selector 231 with the pulse generation circuit 271, the contents stored in the RAM 221 can be changed in parallel with the synchronization establishing operation. Therefore, by changing the stored contents, it is possible to arbitrarily set the specific pattern for synchronization detection and the number of synchronization protection stages.

In the above-described embodiment of the present invention, in order to perform the synchronization detection on the input data having the multi-frame structure, the data regarding each frame read from the RAM 221 is temporarily stored in the RAM 251. The present invention can be applied even in the case where the synchronization detection is performed on the frame data that is input. In this case, omit the RAM 251 and directly output the output of the buffer 245 to the RAM 221.
You may make it return to the side.

Further, in the embodiment, the contents of the RAM 221 are rewritten in parallel with the synchronization detection operation, but the synchronization detection operation and the RAM 221
However, even in this case, there is no change in the advantage that the synchronization pattern and the number of protection stages can be set arbitrarily.

〔The invention's effect〕

As described above, according to the present invention, the synchronization detection is performed by sequentially reading the specific pattern stored in the random access memory and comparing it with the extracted synchronization bit. Since the synchronization pattern and the number of protection stages can be arbitrarily changed by appropriately changing the contents, it is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the synchronization protection circuit of the present invention, FIG. 2 is a block diagram of the synchronization protection circuit according to one embodiment of the present invention, FIG. 3 is an operation timing diagram of one embodiment, and FIG. It is a figure which shows the flow of operation | movement of an Example. In the figure, 111 is a synchronous bit extracting means, 121 is a random access memory, 131 is a comparing means, 141 is an address setting means, 151 is a synchronous detecting means, 211 is a synchronous bit extracting circuit, 221,251 is RAM, 231,235 is a selector, and 233 is An exclusive OR gate, 241, 245 are buffers, 243 is a flip-flop (FF), 261 is a match detection circuit, and 271 is a pulse generation circuit (PG).

Claims (1)

(57) [Claims] 1. A synchronization bit extraction means (111) for extracting a synchronization bit in input data, and a part of a predetermined pattern at each address and its own address in which the next part of the predetermined pattern is stored. A random access memory (121) for storing the data, the predetermined pattern included in the data read from the random access memory (121), and the synchronization bit extracted by the synchronization bit extraction means (111). A comparing unit (131) for detecting these matches, and when a match is detected by the comparing unit (131), selects its own address contained in the data read from the random access memory (121), Address setting means (141) for selecting a predetermined address and inputting it to the random access memory (121) when a mismatch is detected; Synchronization detecting means (151) for detecting the establishment of synchronization when the data read from the access memory (121) reaches a predetermined value, and for detecting the loss of synchronization at other times.
And a synchronization protection circuit, characterized by comprising: