JPS58143500A - Storage device available for interleaving - Google Patents

Abstract

PURPOSE:To improve the use effect of a data control circuit and to facilitate large-scale integration by controlling a connection between the common data input/output terminal of a data control circuit and a memory bank, etc., through a selecting circuit. CONSTITUTION:When an address and a write/read command are applied from a CPU through a control part 4, data control circuits 1-1 and 1-2 equipped with memory banks 2-1, 2-2..., an error correcting and error check bit generating circuit, etc., are specified selectively. Through the selecting circuit 3, connections between the common input/output terminal for the banks 2-1... of the specified circuits 1-1 and 1-2 and for data transfer to the CPU, and a data line 3000 from the banks 2-1... or CPU is controlled. This system wherein the memory banks are not handles for individual memory banks improves the use effect of the data control circuits of the storage device available for interleaving and the number of pins is decreased because of the use of the common output/input terminal to facilitate the large-scale integration of the data control circuits.

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to an interleagueable storage device. Storage devices used in information processing mats often include a data control circuit for performing a partial write operation like a memory circuit. It also improves the access efficiency of memory circuits. It is also widely practiced to divide this into a plurality of memory punctures and perform interleaving operations. In this case, generally, a plurality of data control circuits are provided, and each data control circuit performs the error correction one partial write operation for its own memory puncture.

[However, in the conventional device, the memory bank to which each data control circuit is assigned is fixedly determined in advance. Therefore, there is a drawback that the data control circuit cannot be used to its fullest efficiency. Furthermore, in conventional devices, a data input/output terminal for the memory bank side of the data control circuit and a data input/output terminal for the central processing unit using this memory bank are provided separately, so that the input/output data for each is mutually provided. Avoiding competition. However, this increases the number of data input/output terminals, and when attempting to integrate data control circuits on a large scale, the increase in the number of bins for data input/output terminals makes it difficult to implement. . SUMMARY OF THE INVENTION It is an object of the present invention to provide an interleaveable storage which eliminates the above-mentioned drawbacks of the prior art. Another object of the present invention is to perform an operation of writing 1 to 3 bytes of a part of the storage data width at the same address in a memory 1LCT having an error correction function that performs interleaving. An object of the present invention is to provide a storage device that efficiently performs writing, writing, and writing operations. The device of the present invention consists of a plurality of memory banks and has an error correction system.

[In a storage device that performs data processing, a plurality of data control circuits that share a dawn data input/output terminal and a write data input/output terminal and perform error correction and error correction check pit generation, a plurality of memory banks, and a plurality of memory banks; a data control circuit connected to the bus, and a control section for controlling the plurality of data control circuits and the selection circuit; Correspondence between the data control circuit and the plurality of memory banks [Control is performed to change in response to a request for interleave operation to each of the memory banks. Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. This embodiment includes two data control circuits 1-1 and 1-2.4.
Memory banks 2-1.2-2゜2-3. and 2-
41 selection circuit 3 and control section 4 [includes]. Further, each data control circuit 1 includes a read register 11%, a write register 12, a continuous output/write register 13, and so on, as shown in Figure @2. Syndrome generation circuit 14. Decoding circuit 152 selection circuit 16% WAp correction check bit generation circuit 17, error correction circuit 18. A switching circuit 19 and a driver 20t-include. This data control circuit 1 sends and receives successive data, write data, and partial write data to and from the outside (memory bank and central processing unit 111all), but the human output of these data is all carried out via a common input/output terminal 200. It is done. This leverages the large-scale integration of this data control circuit (
This reduces the number of bins when converting into an LSI (LSI), making it easier to implement. Now, the operations of the storage device of this embodiment for data writing, data reading, and data partial writing are as follows. First, when a central processing unit (not shown, hereinafter referred to as CPU) writes data to a certain memory bank, the CPU informs the control unit 4 of the memory address to be written and that this is a write operation to the memory. specified and data bus 3
00(l) to transfer the write data to the selection circuit 3. Upon receiving the above-mentioned designation, the control section 4 generates necessary control information and outputs the necessary control information to the circuits 1-1 to 1-22, the circuit 3, and the memory bank 2.
-1 to 2-4 [Control and write operation as described below]
Let them do it. First, data control circuit 1-1 (
t or 1-2)': and controls the selection circuit 31 so that the data bus 3000 is connected to the input/output terminal 200 of the data control circuit 1-1. On the other hand, the data control circuit 1-1 (or circuit 1 after 1-2 degrees) is controlled to write data idle state, and as a result, the driver 20 is disabled and becomes a high output impedance, as described above. data input/output terminal 20
The write data transferred to 0 is captured and stored in the write register 12. 1 selection circuit 16 then receives register 12 as its input.
The selected write data is supplied to the error correction check pit generation circuit 17 and the error correction circuit 18. As a result, the circuit 17 generates a WA9 correction check pit for this write data. This is also supplied to the circuit 18, but in the data write operation, the circuit 18 does not make any changes to the supplied write data and check pit. At this point, the switching circuit 19 is controlled to select the output of the circuit 18 without adding the switching circuit 19 to the register 13. Thus, the write data stored in the register 13 and the error correction check pit corresponding to this data are 1
Next, the driver 20 is enabled and the input/output terminal 200 [
The data is transferred to the selection circuit 3 via the filter. At this point, the 1 selection circuit 3 selects the output information from the control circuit 1-1 (t or 1-2) by the control signal from the control unit 4 to the memory bank (this 2 -, and the write data and the error correction check bit therefor are written to the designated memory address of the memory circuit. Next, the operation for data am is as follows. When the CPU reads data from a certain memory address, the CPU specifies to the control unit 4 the memory address to be successively read and that this is an operation to read data continuously from the memory. ' The control unit 4 selects the data control circuit 1-1 (or the data control circuit 1-2) that can be used immediately at that time, and controls the selection circuit 3 to select the memory bank containing the designated memory address 1. The data output line from (this is assumed to be t-2-) is connected to the data input/output terminal 200 of this selected data control circuit 1-1 (t or 1-2) via the selection circuit 3. Do it like this. As a result, the data control circuit 1-1 (or 1-2
Thereafter, the data is transferred to the data input/output terminal 200 of circuit 1). The circuit 1 is controlled in a continuous data acquisition mode, so that the driver 20 is disabled and has a high output impedance, and the information transferred to the input/output terminal 200 is stored in the read register 11. In the data succession operation, the selection circuit 16 is selected to select the output of the register 11 as an input, and as a result,
Nine read data (excluding error correction check bits) stored in the register 11 are supplied to the circuit 18 via the circuit 16'. On the other hand, the output of the register 11 is output from the syndrome generation circuit 14.
A syndrome is generated using the highlighting data and the error correction check bit. The output of the V nodrome of Jin is converted into an error correction designation signal determined by this syndrome in the decoding circuit 15, and is led to the error correction circuit 18, where it is compared with the successive data supplied to circuit l11g to determine the pit correspondence. An exclusive disjunction is taken and error correction is performed. If there is no error in the extracted information, all the outputs of the syndrome generating circuit 14 become 'O', and as a result, the decoding circuit 45
All outputs are also set to 10'. No corrections are made to the read data. Now, the successive data error-corrected in this way is transferred to the switching circuit 19t-, and at this point, the circuit 19 is transferred to the circuit 18.
control to select the output of register 1
3. Then, the driver 20 is enabled and the starting data in the register 13 is transferred to the data input/output terminal 200.
is output to. On the other hand, at this point, the control unit 4 is controlled to connect the output of the terminal 200 to the data path 3000;
The read data corrected in this way is transferred to the CPU. Finally, the operation in the case of one partial write is as follows. The CPU specifies, to the control unit 4, the memory address at which partial write 1 is to be performed, the byte position at which the partial write session is to be performed, and that this is a partial write operation, and the data to which partial write 1 is to be performed is sent via the sound data bus 3000. Selection circuit 3
Transfer to. When the control unit 4 receives the above-mentioned designation, it first selects the data control circuit 1-1 (t or 1) which is currently available for immediate use.
-2), and the data bus 3000 is connected to l! of the data control circuit 1-1. The selection circuit 3 is controlled so as to be connected to the I input/output terminal 200. On the other hand, data control circuit 1-1 (or 1-2. Hereafter circuit 1
) is controlled to the partial write data viewing state, so that the driver 20 is disabled and the high output impedance and voltage, 1! Data input terminal 2 as described in tl
The partial write data transferred to 00 is transferred to the switching circuit 19t?
The data is stored in the read/write register 13 via the read/write register 13. Then, according to the O control information from the control unit 4, the data to be partially written from the specified memory address [including the memory puncture (partially written data)] is read out along with the corresponding error 9 correction check bit, and ξ is selected. The data is transferred to the data input/output terminal 200 of the circuit 1 via the circuit 3. The partially written data including this error 9 correction check bit is stored in the output register 11 from the input/output terminal 200. Next, the selection circuit 16 is controlled by the control information of the control unit 4, and the byte data at the byte position designated for partial writing in the partial writing data stored in the register 13 and the part to be written stored in the register 11 are selected. Byte data at other byte positions in the write data are selectively combined. In this way, the partially replaced data appears on the output of the circuit 16, and the error correction check pit generating circuit 17 generates an error 9 correction check bit for this partially replaced data, and outputs it to the circuit 18 together with the 1 partially replaced data. supplied to On the other hand, the partially written data stored in the register 11 is supplied to a syndrome generation circuit 14, which generates a syndrome if there is an error. This syndrome is converted into an error correction designation signal in the decoding circuit 15 (that is, the error pH of the partially written data: only the bit position to be corrected is %1', and the other bit positions are hol).
This decoding circuit 15 is supplied with information on the I(ite position) to perform partial writing 1 from the control unit 4,
) It is checked whether the correction designation signal exists in a byte part other than the (item) position where one partial write should be performed. If it does not exist (t9), there is no error at all, or even if there is an error. (If it is finally replaced by partial write data because it is at the byte position where partial write should be performed)
, the output of circuit 15 is disabled. In this case, the partial replacement data supplied to the circuit 18 described above and the corresponding error 9 correction chain V tap are transferred to the register 13 in parallel via the switching circuit 19 without any change in the circuit 18. is stored in Thereafter, this data is processed 11K as in the case of normal data writing described above, and the partially written data is found through selection a183 and is stored at the original memory address KI! of the 9th memory bank. will be paid. If the 1@9 correction bit is set in a byte data part other than the byte position where one partial write is to be performed in one circuit 15, the circuit 15 is enabled, and this erroneous 9 correction pit is set in the circuit 1118 of the corresponding bit position. In order to correct the partial replacement data supplied to
The syndrome that occurred in 4 is the tttm approx. 18 approx. 8
Then, a bitwise exclusive OR is performed on the error correction check bits for the partial replacement data. The partial replacement data whose errors have been corrected and the correction check pits corresponding thereto are obtained in parallel at the output of the circuit 118. These are the switching circuit 19
11-, the data is once stored in the register 13, and thereafter stored in the memory address specified by the partial write t in the same manner as described above, and the partial write operation is completed. In the circuit of this embodiment that operates as described above, the data control section till -
Connections with memory banks 2-1 to 2-4 can be freely changed and operated as necessary. Figure 11!3 shows several nt time charts of such combinations. Figure 3: Prisoners are memory bank 2-1 and memory bank 2-
In this case, as shown in the figure, the partial write request control circuit for memory bank 2-1 generates a partial write request for memory bank 2-1 consecutively every clock in synchronization with successive clocks. 1-2 (In a partial write operation, the data stored in the read register 11 must be held for a period longer than the t-1 write cycle, so the Ru2
(It is not possible to process two partial write requests using the same data control circuit.) In contrast, in FIG. 3(b), a partial write request to memory bank 2-1 is made at the beginning of the clock, then a full write request (normal write request) to memory bank 2-2 is made, and then , shows a time chart when there is a partial write request to memory bank 2-3 again.
As shown in c), parallel processing using the same data control unit 111-1 (or 1-2) becomes difficult. however,
In this case, the data control circuit 1-1 may first be sent to the CPU or memory bank 2-1 via the data bus 3000.
Partial write data for one memory bank 2-2 is stored in the register 12, and then all write data sent from the CPU to the memory bank 2-2 is stored in the register 13. In this state, the partial write data is retrieved from the designated memory bank 2-1 and stored in the register 11, and before the above-mentioned portion 1llIl' replacement operation is performed, all the write data stored in the register 13 is extracted. is the selection circuit 16
% error correction check bit generation times W&17. The error correction check bit Kurayoshi is used in the error correction circuit 18 to generate all write data, and by storing this again in the register 13, the operation shown in (c) in Figure 3 can be performed. . In this way, it is possible to process partial write requests and full write requests to other memory banks that occur one clock later using the same data control circuit. The third partial write request that occurs subsequently may be sent to another data control circuit 1-2 (or 1-1). @Figure 3 (q shows the case where write requests occur in successive clocks to different memory banks in the order of partial write, full write, full write, and partial write.As is clear from the previous explanation, It is used for the first two data control circuits 1-1 (or 1-2)', and for the other two data control circuits 1-2 (i or 1-1). In the above-mentioned M1 column, an example of the configuration of two data control circuits and four memory banks was shown. Of course, the number is not limited to this. As described above, the present invention uses a plurality of data control circuits that share data input/output terminals. Data writing--request It is possible to provide a flexible memory interleaving storage device that can be selected most efficiently depending on the situation of a data partial write request or a data continuation request from a memory bank. In addition, it is suitable for large-scale integration as a data control circuit with a small number of bins for input/output data. It is possible to provide a circuit configuration that performs an interleave operation by using an error correction and error correction check pit generation t-row data control circuit that can share data and check pit input/output bins for reading and writing. This makes it possible to improve the performance of the storage device.

[Brief explanation of the drawing]

@1 Figure is a block diagram showing one embodiment of the present invention. Figure 2 is a block diagram showing details of the data control circuit used in this embodiment, and Figures (5), (B) and (q) are time charts for explaining the operation of this embodiment. , 1.1-1.1-2... Data control circuit, 2-1 to 2-4... Memory bank, 3
. . . Selection circuit, 4 . . . Control unit, 11.
...Read register, 12...Write register, 13...Read/write register, 14
...Syndrome generation circuit, 15...
Decode circuit, 16... Selection circuit, 17...
...Error correction check bit generation circuit, 18...
...Error correction circuit, 19...Switching circuit% 2
0... Driver. Figure 1

Claims (1)

[Scope of Claim] In a storage device that performs error correction from a plurality of memory punctures. a plurality of data control circuits that share a continuous data input/output terminal and a write data input/output terminal and perform error correction and error correction check bit generation; a plurality of memory punctures; and the plurality of data control circuits. With multiple interconnected selection circuits. It has a control section that controls the plurality of data control circuits, the plurality of memory punctures, and the selection circuit. The control unit is configured to control the plurality of O data control circuits and the plurality of memory punctures to be controlled in response to an interleaving operation for each memory bank. t-Characteristic storage device.