USRE45857E1 - External storage device and memory access control method thereof - Google Patents

External storage device and memory access control method thereof Download PDF

Info

Publication number
USRE45857E1
USRE45857E1 US13475679 US201213475679A USRE45857E US RE45857 E1 USRE45857 E1 US RE45857E1 US 13475679 US13475679 US 13475679 US 201213475679 A US201213475679 A US 201213475679A US RE45857 E USRE45857 E US RE45857E
Authority
US
Grant status
Grant
Patent type
Prior art keywords
data
sector
non
semiconductor memory
volatile semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US13475679
Inventor
Takayuki Tamura
Shigemasa Shiota
Kunihiro Katayama
Masashi Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Emergence Memory Solutions LLC
Original Assignee
Solid State Storage Solutions Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date
Family has litigation

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Abstract

A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.

Description

CROSS REFERENCE TO RELATED APPLICATION

This is a reissue application of U.S. application Ser. No. 11/599,388, now U.S. Pat. No. 7,721,165, which is a continuation of U.S. application Ser. No. 10/748,156, filed Dec. 31, 2003 now U.S. Pat. No. 7,234,087, which is a continuation of U.S. application Ser. No. 09/750,707, filed Jan. 2, 2001 (now U.S. Pat. No. 6,701,471), which is a continuation of U.S. application Ser. No. 09/544,609, filed Apr. 6, 2000 (now U.S. Pat. No. 6,199,187), which is a division of U.S. application Ser. No. 09/046,705, filed Mar. 24, 1998 now abandoned, which is a continuation of U.S. application Ser. No. 08/679,960, filed Jul. 15, 1996 (now U.S. Pat. No. 5,732,208). This application relates to and claims priority from Japanese Patent Application No. 07-179075, filed on Jul. 14, 1995. The entirety of the contents and subject matter of all of the above is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an external storage device of a computer using, for example, a static storage device, and more particularly relates to an external storage device for processing error detection and error correction of sector data at a high speed when sector data having an arbitrary byte width are accessed continuously according to a size of a sector unit.

2. Description of Related Art

With regard to background art, in order to simultaneously realize an improvement in reliability and high speed access in memory control, as disclosed in Japanese Patent Laid-Open No. Hei 6-105443 (1994), there is a system where data of an x-byte width outputted from a memory are divided into an odd number part (x/2 byte width) and an even number part (x/2 byte width), and regarding each of the odd number part and the even number part, error detection and error correction are performed using error correcting codes, and data of an x/2 byte width as outputted from the odd number part and the even number part are continuously outputted to a system bus of an x/2 byte width by an interleave control method.

In order to perform the error detection and the error correction for sector data having an m-byte (e.g., 512 byte) width, the sector data of an m-byte width must be divided into an n-byte (e.g., one byte) unit for m/n times (m is a multiple of n) and then inputted to error correcting means.

However, since error detection and error correction in the background art as described above are performed for data having a same byte width as that of the system bus, a differing byte arrangement cannot be applied as it is to error detection and error correction for sector data having an m-byte width larger than the byte width of the system bus. Moreover, as a further disadvantage in the background art as above described, both the odd number part and the even number part require individual error correcting means.

The teachings of each of any above- or below-listed art are herein incorporated by reference.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an external storage device where a time required for error detection and error correction is reduced when error detection and error correction are performed for sector data having an m-byte width larger than the byte width of the system bus, and to realize a memory access at a high speed.

Another object of the present invention is to provide an external storage device where a time required for error detection and error correction is reduced using a single error correcting means, and to realize a memory access at a high speed.

In order to attain the foregoing objects, the present invention provides an external storage device comprising: a system interface section for conducting an interface with a host computer; error correcting means for performing error detection and error correction for sector data constituted by data having a byte number larger than that of a bus width of a system bus connecting the system interface section and the host computer; a first memory and a second memory as static storage devices each having a memory bus with a same bus width as that of the system bus for storing sector data; and control means for controlling a reading and writing operation of sector data from the host computer to the first memory and the second memory, wherein in response to a write command from the host computer, the control means stores a plurality of sector data attendant on the write command in the size of a sector unit alternately in the first memory and the second memory, and in response to read command from the host computer, the control means reads out the first sector data among a plurality of sector data required by the read command from the first memory and supplies the read-out sector data to the error correcting means, and then the control means reads out the sector data of the first memory and the second memory simultaneously, so that while the N-th (where N is a natural number) sector data from one of the first memory and the second memory are transferred to the system interface section, the (N+1)th sector data from the other are transferred to the error correcting means.

In this preferred external storage device, data changing means selectively connects the memory bus of the first memory to one of the system interface section and the error correcting means, and also selectively connects the memory bus of the second memory to the other, and during the read access from the host computer, the control means alternately controls the data changing means so as to selectively and alternately read out the sector data of the first memory and the second memory.

In a write access of sector data from the host computer to the first and second memories, a write buffer for temporarily storing the sector data may be provided to effect storage of the sector data in the first and second memories through the write buffer.

In another embodiment, in place of the first memory and the second memory, a memory having a memory bus width of twice that of the system bus for storing sector data may be used. In this case, in response to write command from the host computer, the control means stores odd-numbered sector data (among a plurality of sector data) attendant on the write command using, for example, an upper side of the memory bus and memory, and also stores even-numbered sector data using, for example, a lower side of the memory bus and memory. In response to a read command from the host computer, the control means reads out the first sector data among a plurality of sector data required by the read command from the upper side of the memory and supplies the readout sector data to the error correcting means, and then the control means reads out the sector data at the upper side and the lower side of a memory address simultaneously, so that while the N-th (where N is a natural number) sector data from one of the upper side and the lower side of the memory address are transferred to the system interface section, the (N+1)th sector data from the other are transferred to the error correcting means.

Also in a memory access control method of an external storage device according to the present invention, the external storage device having a static storage device storing sector data and comprising a first memory storing odd-numbered sector data of sectors of a plurality of continuous sectors of an access object and a second memory storing even-numbered sector data of sectors as the static storage device and error correcting means performing error detection and error correction for the sector data are used. When write access is performed from a host computer to the plurality of continuous sectors, odd-numbered sector data together with error correcting codes are stored in the first memory and also even-numbered sector data together with error correcting codes are stored in the second memory alternately in a size of a sector unit. When a read access is performed from the host computer to the plurality of continuous sectors, the first sector data are read out from the memory and error detection and error correction are performed by the error correcting means and while the first sector data having the error detection and error correction finished are transferred from the first memory to the host computer, the second data are simultaneously read out from the second memory and transferred to the error correcting means. Subsequently, while the second data having the error detection and error correction finished are transferred from the second memory to the host computer, third sector data are simultaneously read out from the first memory and transferred to the error correcting means. In a similar manner, while the N-th sector data having the error detection and error correction finished are transferred to the host computer, the (N+1)th sector data are simultaneously read out and transferred to the error correcting means.

According to the present invention, control means (e.g., a microprocessor) can store a plurality of sector data of a write object in a memory so that the N-th sector data and the (N+1)th sector data can be read out simultaneously. Thereby, at any time, the N-th sector data can be outputted to a system bus by data changing means, and (N+1)th sector data can be simultaneously outputted to error correcting means. Consequently, since a time required for the error detection and error correction for the (N+1)th data can be performed simultaneously during the time the Nth data are outputted to the system bus, the time (as experienced by the external storage arrangement) required for the error detection and error correction for the sector data can be reduced apparently (i.e., made transparent to a host computer).

Also since the error detection and error correction are always executed only for singular sector data which is subsequent to the sector data currently being transferred to the host computer, a single error correcting means may be used well.

The foregoing and other objects, advantages, manner of operation, novel features and a better understanding of the present invention will become apparent from the following detailed description of the preferred embodiments and claims when read in connection with the accompanying drawings, all forming a part of the disclosure hereof this invention. While the foregoing and following written and illustrated disclosure focuses on disclosing embodiments of the invention which are considered preferred embodiments at the time the patent application was filed in order to teach one skilled in the art to make and use the invention, and to otherwise satisfy the best mode disclosure requirements under U.S. patent law, it should be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The following represents brief descriptions of the drawings, wherein:

FIG. 1 is a block diagram showing a system configuration of an external storage device of the invention.

FIG. 2 is a block diagram showing a configuration of a system interface section 13.

FIG. 3 is a block diagram showing a configuration of data changing means 11.

FIG. 4 is a diagram showing a truth table of a read data selecting circuit 116.

FIG. 5 is a diagram showing a truth table of an error correcting means input data selecting circuit 117.

FIGS. 6-11 are flow charts showing operation of a host computer 2.

FIG. 12 is a block diagram showing a system configuration of another embodiment of an external storage device of the invention.

FIG. 13 is a block diagram showing a configuration of data changing means.

FIG. 14 is a block diagram showing a system configuration of still another embodiment of an external storage device of the invention.

FIG. 15 is a block diagram showing a configuration of data changing means 93.

FIG. 16 is a timing chart showing an operation example of a write processing in an embodiment of the present invention.

FIG. 17 is an explanation diagram of a first memory 4 and a second memory 5.

FIG. 18 is a timing chart showing an operation example of a read processing in an embodiment of the present invention.

FIG. 19 is a timing chart subsequent to the timing chart in FIG. 18.

FIG. 20 are views of a memory card containing an external storage device of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before beginning a detailed description of the subject invention, mention of the following is in order:

When appropriate, like reference numerals and characters are used to designate identical, corresponding or similar components in differing figure drawings.

Embodiments of the present invention will be described using the accompanying drawings as follows. More particularly, FIG. 1 is a block diagram showing a system configuration of a first embodiment of an external storage device 1000 according to the present invention. A memory control unit 1 writes or reads sector data to a first memory 4 and a second memory 5 according to a command from a host computer 2, such memory control unit receiving the command of the host computer 2 by a control signal 22 and an external bus 32.

The host computer 2 is connected to a system bus 3 by a host computer bus 31, and performs read and write operations of the sector data to the memory control unit 1 using the control signal 22 and the system bus 3.

The first memory 4 and the second memory 5 are storage means storing the sector data respectively, and a flash memory is used in a preferable embodiment although use of the present invention is not limited thereto. The flash memory is a known non-volatile semiconductor memory where electric erase and rewrite of data are possible in the size of a sector unit of a predetermined byte number (e.g., 512 bytes). However, the present invention can be applied also to other memory device and arrangement, and especially static storage devices.

A local bus 6 is a bus connecting the memory control unit 1, a write buffer 7 and a microprocessor 8. The write buffer 7 is a storage means for temporarily storing the sector data written by the host computer 2, and is connected to the local bus 6 by a write buffer bus 61. The microprocessor 8 is connected to the local bus 6 by a microprocessor bus 62, analyzes the command set to the memory control unit 1 by the host computer 2 and sets the operation to be performed by the memory control unit 1. In this preferred embodiment, when a bus width of the system bus 3 is, for example, M bytes, a bus width of the local bus 6 is also M bytes to match that of the system bus 3, and also, a bus width of each of a first memory bus 111 and a second bus 112 is M bytes to match that of the system bus 3.

Data changing means 11 selectively directs the sector data from the first memory bus 111 and the second memory bus 112 onto an ECC bus 113 and an internal data bus 114. Error correcting means 12 generates emir correcting codes for sector data for output to the internal data bus 114, also performs error detection and error correction of sector data input from the ECC bus 113, and informs the microprocessor 8 of the results of the error detection and error correction using a signal line 19. A system interface section 13 receives any command fur memory access from the host computer 2 along the control signal 22 and the external bus 32. In response to such memory access command, the system interface section 13 outputs an interrupt signal 131 to the microprocessor 8. Also the system interface section 13 generates an appropriate read signal 132, a write signal 133, a transfer finishing signal 134 and a timing signal 135 to control read/write of sector data by the control signal 22.

When the host computer 2 instructs writing of sector data, the write signal 133 is outputted and the sector data from the host computer 2 are stored from the internal data bus 114 into the write buffer 7 in accordance with a timing of the timing signal 135. Also when the host computer 2 instructs reading of sector data, the read signal 132 is outputted and the sector data of the first memory bus 111 or the second memory bus 112 are read out in accordance with a timing of the timing signal 135 and directed to the internal data bus 114 by the data changing means 11 and outputted from the system interface section 13 to the computer 2. Further the sector data are outputted to the host computer 2, and at the same time the sector data (e.g., next sequential sector data) of the first memory bus 111 or the second memory bus 112 are directed into the ECC bus 113 by the data changing means 11 (under control of a signal from the microprocessor 8 along a signal line 18) and error detection and error correction are performed in the error correcting means 12.

In a preferred embodiment, components along a lower side of the system interface section 13, or contained within the outline designated by 1000 (in FIG. 1) can be contained within a memory card (e.g., flash memory card), views of which are shown in FIG. 20.

FIG. 2 is a block diagram showing a configuration of the system interface section 13. A data buffer 136 performs buffering of sector data from the external bus 32 and sector data from the internal data bus 114. The command from the host computer 2 is set to an access setting register 137 along the line 22. The command indicates the front address of the sector data to be accessed, a type of access (read or write) and the number of sectors (e.g., range of sector numbers or addresses) to be accessed. When the host computer 2 sets the command to the access setting register 137, the access setting register 137 outputs an interrupt signal 131. Also the access setting register 137 outputs a read signal 132 or a write signal 133 responsive to the set command. A control signal decoding section 138 outputs a transfer finishing signal 134 and a timing signal 135 from a control signal 22. The transfer finishing signal 134 is outputted when the access to data of one sector is finished. The timing signal 135 is generated from the control signal 22 when the host computer 2 reads or writes the sector data. A status register 139 stores data indicating the state of the memory control unit 1. When the interrupt signal 131 is outputted and when the transfer finishing signal 134 is outputted, the status register 139 is set to the busy state. Also the status register 139 is set to the ready state by the microprocessor 8. When the status register 139 is in the busy state, the host computer does not read and write the sector data.

FIG. 3 is a block diagram showing configuration of the data changing means 11. A data selection setting register 115 is a storage means set by the microprocessor 8 using, for example, a signal along a signal line 18, where information to select the data to be outputted to the ECC bus 113 and the internal data bus 114 from the first memory bus 111 or the second memory bus 112 is set. A read data selecting circuit 116 selects data to be outputted to the internal data bus 114 from the first memory bus 111 or the second memory bus 112 according to a content of the data selection setting register 115. An error correcting means input data selecting circuit 117 selects data to be outputted to the ECC bus 113 from the first memory bus 111 or the second memory bus 112 according to a content of the data selection setting register 115.

FIG. 4 shows a truth table of the read data selecting circuit 116. Data to be outputted to the internal data bus 114 are selected from the first memory bus 111 or the second memory bus 112 according to a content of the data selection setting register 115. FIG. 5 shows a truth table of the error correcting means input data selecting circuit 117. Data to be outputted to the ECC bus 113 are selected from the first memory bus 111 or the second memory bus 112 according to content of the data selection setting register 115.

When a bus width of the system bus 3 is one byte, operation of the host computer 2 with regard to reading or writing of the sector data will be described using a flow chart as follows. More particularly, FIG. 6 in a flow chart when the host computer 2 reads or writes the sector data. First, in step S001, a command is set to the access setting register 137 within the system interface section 13. The command includes the sector number of the access start sector and the number of sectors to be accessed continuously. And then the status register 139 is supervised (step S002) by the host computer 2. If the status register 139 is set in the ready state, the host computer 2 reads or writes the data buffer 136 in the size of a one byte unit (step S003). Operation of step S003 is repeated for data of one sector until a read or write operation is finished (step S004). If a read or write operation for all sector data is not finished (“No” branch of step S005), the operations from steps S002 to S004 are repeated, and when a read or write operation for all sector data is finished, the read or write operation of the host computer 2 is finished.

FIG. 7 to FIG. 11 are flow charts showing operation of the microprocessor 8. First, in step S101, the microprocessor 8 supervises the outputting of an interrupt signal 131 indicating that the host computer 2 has set a command to the access setting register 137. If the interrupt signal 131 is outputted, the microprocessor 8 reads out the access setting register 137 and analyzes the command set by the host computer 2 (step S102). Subsequently in step S103, if a type of access requested is a “write” operation, step S104 is executed, and if a “read” operation is requested, operation of a flow chart shown in FIG. 9 is executed.

When command of the access setting register 137 indicates a “write” operation, in order that the sector data to be written by the host computer 2 are stored in the write buffer 7, the microprocessor 8 outputs an address 81 to the write buffer 7 (step S104), and sets a ready state to the status register 139 (step S105). Subsequently, if data of one sector are stored from the host computer 2 to the write buffer 7, a transfer finishing signal 134 is outputted from the control signal decoding section 138. If the microprocessor 8 detects that the transfer finishing signal 134 is outputted in step S106, error correcting codes stored in the error correcting means 12 are read out (step S107). Subsequently, the microprocessor 8 executes operation of a flow chart shown in FIG. 8.

More particularly, turning now to FIG. 8, if the sector data stored in the write buffer 7 are the (2N−1)th (that is, odd-numbered) sector data, the first memory address 82 for the first memory 4 is outputted (step S109), and sector data are transferred from the write buffer 7 to the first memory 4 and further the error correcting codes are stored in the first memory 4 (step S110). Conversely, if the sector data stored in the write buffer 7 are the 2N-th (that is, even-numbered) sector data, the second memory address 83 for the second memory 5 is outputted (step S111), and sector data are transferred from the write buffer 7 to the second memory 5 and further the error correcting codes are stored in the second memory 5 (step S112).

FIG. 17 shows a state of data stored in the first memory 4 and the second memory 5. As clearly seen from FIG. 17, data of one sector (here 512 bytes) and error correcting codes generated therefore are stored in each address of the first and second memories. Error correcting codes in this preferred embodiment consist of one code (here 3 bytes) given to the data of one sector.

When a writing operation of all sector data from the host computer 2 is finished, the microprocessor 8 repeats operations from step S101. When it is not finished, operations from step S104 to step S112 as above described are repeated (S113).

If the command of the access setting register 137 indicates a “read” operation, operation of a flow chart shown in FIG. 9 is executed. More particularly, turning now to FIG. 9, first, the host computer 2 performs error detection and error correction for sector data to be read first. Since (2N−1)th (i.e., odd-numbered) sector data are stored in the first memory 4, in order to input the first sector data to the error correcting means 12, the microprocessor 8 sets a ‘1’ to the data selection setting register 115 (step S114). Thereby in the memory control unit 1, sector data read from the first memory 4 are directed within the data changing means 11 into the ECC bus 113 and are then outputted, and error detection and error correction for the sector data read from the first memory 4 are performed in the error correcting means 12. Here, from the first memory 4, the sector data and the error correcting codes subsequent thereto are outputted and the error correcting codes are inputted to the error correcting means 12. Thereby in the error correcting means 12, the sector data read from the first memory 4 are decoded and any error therein can be detected. Also in the memory control unit 1, if outputting of the sector data read from the first memory 4 are finished for the error correcting means 12, the transfer finishing signal 134 is outputted to the microprocessor 8. If the microprocessor 8 detects that the transfer finishing signal 134 is outputted (step S115), the decoding results stored in the error correcting means 12 are read out (step S116), and a decision is effected regarding whether any error is generated (i.e., detected) or not (step S117). If an error is generated, the microprocessor 8 makes the error correcting means 12 start the error correction processing thereby to determine an error position and correction pattern, and returns and writes correction results to the sector data having error generated and stored in the first memory 4 (step S118). If no error is generated, process is advanced to step S119 in FIG. 10.

More particularly, in turning to FIG. 10, in step S119, the microprocessor 8 confirms whether the sector data to be outputted to the host computer 2 are the (2N−1)th (i.e., odd-numbered) data or not. Instep S120, the microprocessor 8 sets ‘0’ to the data selection setting register 115, so that the (2N−1)th sector data are outputted to the host computer 2 and also the 2N-th sector data are inputted to the error correcting means 12. In a next step S121, an address of sector data to be outputted to the host computer 2 is outputted to the first memory address 82, and an address of the sector data performing error detection and error correction is outputted to the second memory address 83.

In step S122, the microprocessor 8 sets “1” to the data selection setting register 115, so that the 2N-th sector data are outputted to the host computer 2 and also the (2N+1)th sector data are inputted to the error correcting means 12. In step S123, an address of the sector data performing error detection and error correction is outputted to the first memory address 82, and address of the sector data to be outputted to the host computer 2 is outputted to the second memory address 83. Then, the microprocessor 8 sets the status register 139 to the ready state (step S124).

More particularly, the status register 139 is set to the ready state, thereby the host computer 2 reads the sector data for the memory control unit 1. In step S125, a decision is effected regarding whether the transfer finishing signal 134 is outputted or not. If a reading operation for data of one sector is finished, a transfer finishing signal 134 is outputted from the control signal decoding section 138 of the memory control unit 1. More particularly, the transfer finishing signal 134 is outputted, thereby the microprocessor 8 reads out the decoding results stored in the error correcting means 12 (step S126), and a decision (step S127; FIG. 11) is effected regarding whether an error is generated (i.e., detected) or not. If an error is generated, the microprocessor 8 makes the error correcting means 12 start an error correction processing to thereby determine an error position and correction pattern, and the correction results are returned and written to the sector data in the first memory 4 or the second memory 5 (step S128) having such error therein. If no error is generated, the process is advanced to step S129. When the host computer 2 finishes reading of all sector data, the microprocessor 8 repeats operations from step S101, and when it is not finished, operations are repeated from steps S119 to S128 as above described (step S129).

Next, a specific processing example of the device of FIG. 1 will be described using the timing charts shown in FIG. 16, FIG. 18 and FIG. 19. More particularly, FIG. 16 shows a write operation writing a sector data from the host computer 2 to the memories 4, 5. At the time “t0,” if a write command is set from the host computer 2 to the access setting register 137, at the time “t1,” an interrupt signal 131 is generated and such interrupt is applied to the microprocessor 8. Also at the time “t1,” the status register 139 is changed to indicate a busy signal. Then, at the time “t2,” the status register 139 is changed to indicate a ready signal and the microprocessor 8 generates an address 81 to the write buffer 7. At the time “t3” or later, data 1 to 512 representing 512 bytes are written in sequence one byte at a time into the assigned address positions of the write buffer 7 according to the timing signal 135. Also the data 1 to 512 representing 512 bytes are inputted from the internal data bus 114 to the error correcting means 12 according to the timing signal 135, and the error correcting means 12 generates error correcting codes. If the final data of 512 bytes are written at the time “t4,” a transfer finishing signal 134 is outputted at the time “t5.” Then, the sector data stored in the write buffer 7 in such manner are written in the first memory 4 or the second memory 5 as described in FIG. 8. The storage results stored within the memories 4, 5 become as shown in FIG. 17.

FIG. 18 and FIG. 19 show a read operation reading the sector data of the memories 4, 5 as requested from the host computer 2. First in FIG. 18, at the time “t6,” a read command is set from the host computer 2 to the access setting register 137, and then at the next time “t7,” an interrupt signal 131 is generated and the interrupt is applied to the microprocessor 8. In this example, data of plural sectors at the address “100” or later shall be read out continuously. At a time “t8,” the address “100” of the first sector to be read out is given to the first memory address 82, and at a time “t8” or later, the data of 512 bytes and the accompanying error correcting codes of 3 bytes are read out from the first memory bus 111 in sequence one byte at a time according to the timing signal 135. These data are outputted to the ECC bus 113 and then inputted to the error correcting means 12.

Next, referring to FIG. 19, in order that the data of the first sector with the error check finished are outputted in turn to the internal data bus 114 (that is, to the side of the host computer 2), a directing state of the data changing means 11 is reversed. At a time “t9,” the address of the first memory address 82 remains “100” and the address of the second memory address 83 is made “101.” At a time “t10” or later, the sector data of the address “100” are read out again from the first memory 4. The sector data are outputted to the internal data bus 114. Simultaneous with outputting of the “100” address sector data, the data of 512 bytes of the second sector and the accompanying error correcting codes of 3 bytes are read out in sequence one byte at a time from the address “101” of the second memory 5, and are then outputted to the ECC bus 113 communicating with the error correcting means 12. After the reading of both sector data are finished, at the time “t1,” in turn, the address “101” of the second memory 5 having an error check finished is outputted to the memory address 82 of the first memory 4 and the second memory address 5 remains at the address “101.” The directing state of the data changing means 11 is then reversed. Thereby at the time “t12” or later, the sector data of the address “101” are outputted to the internal data bus 114, and at the same time the sector data of the address “102” corresponding to a next sector are outputted to the side of the ECC bus 113. Thus during reading of data of continuous sectors, the sector data are obtained continuously on the internal data bus 114. As a result, it appears to the host computer 2 as if the time for error check processing by the error correcting means 12 did not exist.

As above described, according to this embodiment, the microprocessor 8 stores odd-numbered sector data stored in the write buffer 7 to the first memory 4 and also stores even-numbered sector data to the second memory 5. Accordingly, since the host computer 2 can read the N-th sector data and simultaneously can output the (N+1)th sector data to the error correcting means 12, the time required for error detection and error correction to the (N+1)th sector data can be reduced apparently (i.e., made transparent to the host computer).

FIG. 12 is a block diagram showing a system configuration of another embodiment of an external storage device according to the present invention. More particularly, except for a memory 9, a memory bus 91 and data changing means 92, this embodiment has the same configuration as that of FIG. 1 and performs a same operation. A memory 9 has a bus width which is twice as large as that possessed by each of the first memory 4 and the second memory 5 in FIG. 1, and is connected by a memory bus 91 to data changing means 92 of a memory control unit 1 and a local bus 6. The data changing means 92 selectively directs upper data and lower data from the memory bus 91 into an internal data bus 114 and an ECC bus 113.

FIG. 13 is a block diagram showing a configuration of the data changing means 92. A data selection setting register 115, a read data selecting circuit 116 and an error correcting means input data selecting circuit 117 perform the same operation as that shown and described with respect to the block diagram of FIG. 3. Data from the memory bus 91 are inputted as upper data 911 and lower data 912 to a read data selecting register 116 and an error correcting means input data selecting circuit 117. The read data selecting register 116 outputs the upper data 911 or the lower data 912 to the internal data bus 114 according to a content of the data selection setting register 115. Also the error correcting means input data selecting circuit 117 outputs the upper data 911 or the lower data 912 to the ECC bus 113 also according to a content of the data selection setting register 115.

That is, also for the memory 9 having the bus width twice as large as that of the system bus 3, since the microprocessor 8 stores the (2N−1)th (odd-numbered) sector data stored in the write buffer 7 to upper bit memory positions and stores the 2N-th (even-numbered) sector data to lower bit memory positions on the same memory bus, the host computer 2 can simultaneously output the N-th sector data to the internal data bus 114 and can output the (N+1)th sector data to the error correcting means 12. Consequently, a time required for the error detection and the error correction to the (N+1)th sector data can be reduced apparently (i.e., made transparent to a host computer 2).

FIG. 14 is a block diagram showing a system configuration of another embodiment of an external storage device according to the present invention. In the configuration of FIG. 14, the write buffer 7 shown in the block diagram of FIG. 1 is not used. That is, the sector data written by a host computer 2 are not stored temporarily to the write buffer, but are written directly to a first memory 4 or a second memory 5. Therefore when the host computer 2 writes the sector data, data changing means 93 outputs data by directing the same from an internal data bus 114 to a first memory bus 111 or a second memory bus 112.

More particularly, FIG. 15 is a block diagram showing a configuration of the data changing means 93. A data selection setting register 115, a read data selecting circuit 116 and an error correcting means input data selecting circuit 117 perform the same operation as that shown and described with respect to the block diagram of FIG. 3. A write data selecting circuit 118 outputs data of an internal data bus 114 by directing the same to a first memory bus 111 or a second memory bus 112 according to a content of the data selection setting register 115. When the data selection setting register 115 is ‘0’, the sector data of the internal data bus 114 are outputted to the first memory bus 111, and when the data selection setting register 115 is ‘1’, the sector data of the internal data bus 114 are outputted to the second memory bus 112.

That is, since the write data selecting circuit 118 of the data changing means 11 outputs the (2N−1)th (odd-numbered) sector data to the first memory bus 111 and outputs the 2N-th (even-numbered) sector data to the second memory bus 112, the (2N−1)th sector data can be stored in the first memory 4 and the 2N-th sector data can be stored in the second memory 5. Thereby since the host computer 2 can read the N-th sector data and simultaneously can output the (N+1)th sector data to the error correcting means 12, the time required for the error detection and the error correction to the (N+1)th sector data can be reduced apparently (i.e., made invisible to the host computer 2).

This concludes the description of the preferred embodiments.

Although the present invention has been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject data changing means arrangement within the scope of the foregoing disclosure, the drawings and the appended claims without departing from the spirit of the invention, e.g., the following represents a non-exhaustive list of modifications which might readily be apparent to one skilled in the art to which the present invention is directed: data obtained from the first memory or second memory may be temporarily stored in buffer memories before outputting to the internal data bus or error correcting means; and, the data within the error correcting means which has been subjected to error detection and correction may be outputted onto the internal data bus rather than performing a redundant reading from the memory.

In addition to variations and modifications in the component parts and/or arrangements, uses with alternative non-static memories or with internal memories will also be apparent to those skilled in the art. More particularly, while the above disclosure has discussed applications of the subject combination arrangement with respect to static memories, it will be apparent to those skilled in the art that each of the subject combination arrangements are not so limited to such usage, but instead, could find application in a tremendous number of other uses, e.g., the combination arrangement disclosed above might have application with respect to dynamic memories.

Claims (27)

The invention claimed is:
1. A storage device, comprising:
a non-volatile semiconductor memory which is electrically erasable and which has first and second portions coupled to first and second buses;
a system interface coupled with an external host system; and
a controller reading data from said non-volatile semiconductor memory and transmitting said data to said host system via said system interface in response to a read command received by said system interface from said host system; and
wherein said controller starts reading (N+n)th sector data from said first portion of said non-volatile semiconductor memory via said first bus, while said controller transmits Nth sector data that has been read from said second portion of said non-volatile semiconductor memory via said second bus, to said host system via said system interface, in response to said read command for successive sector data, where N and n are integers.
2. A storage device as claimed in claim 1,
wherein said controller, in response to said read command for successive sector data,
reads said Nth sector data from said non-volatile semiconductor memory into said controller,
carries out data processing for said Nth sector data,
transmits said Nth sector data after said data processing to said host system via said system interface,
starts reading said (N+n)th sector data from said non-volatile semiconductor memory for said data processing for said (N+n)th sector while said controller transmits said Nth sector data after said data processing to said host system via said system interface,
carries out said data processing for said (N+n)th sector data, and
transmits said (N+n)th sector data after said data processing to said host system via said system interface.
3. A storage device as claimed in claim 2,
wherein said data processing is error correction processing of successive sector data.
4. A storage device as claimed in claim 1, comprising an error correction circuit for said successive sector data, and
wherein said controller starts transmitting said (N+n)th sector data from said non-volatile semiconductor memory to said error correction circuit, while said controller transmits said Nth sector data that has been carried out error correction processing by said error correction circuit, to said host system via said system interface.
5. A storage device as claimed in claim 1,
wherein said “n” is one.
6. A storage device as claimed in claim 1,
wherein a size of said sector data is 512 bytes.
7. A storage device as claimed in claim 1,
wherein said non-volatile semiconductor memory is a flash memory.
8. A storage device as claimed in claim 1,
wherein said non-volatile semiconductor memory is electrically erasable in a size of a sector unit.
9. A storage device, comprising:
a non-volatile semiconductor memory which is electrically erasable and which has first and second portions coupled to first and second buses;
a system interface coupled with an external host system; and
a controller reading data from said non-volatile semiconductor memory and transmitting said data to said host system via said system interface in response to a read command received by said system interface from said host system; and
wherein said controller carries out data processing for sector data that has been read from said non-volatile semiconductor memory, and
wherein said controller starts reading (N+n)th sector data from said first portion of said non-volatile semiconductor memory via said first bus for said data processing for said (N+n)th sector data, while said controller transmits Nth sector data that has been carried out said data processing after having been previously read from said second portion of said non-volatile semiconductor memory via said second bus, to said host system via said system interface, in response to said read command for successive sector data, where N and n are integers.
10. A storage device, comprising:
a non-volatile semiconductor memory which is electrically erasable and where data is stored in sector data divisions, where said non-volatile semiconductor memory has a first memory section and a second memory section storing alternating sectors of the data, respectively, and where said first memory section and said second memory section are accessed by first and second buses, respectively;
a system interface coupled with an external host system; and
a controller reading successive sectors of said data from said non-volatile semiconductor memory, responsive to a read command for successive sectors from said host system, and transmitting said data to said host system via said system interface;
wherein in response to said read command for successive sector data, said controller reads an (N+n)th sector of sector data of said data, from said first memory section of said non-volatile semiconductor memory via said first bus, while said controller transmits an Nth sector of sector data of said data, that has been read from said second memory section of said non-volatile semiconductor memory via said second bus, to said host system via said system interface, where N and n are integers.
11. A storage device as claimed in claim 10,
wherein said controller, in response to said read command for successive sectors,
reads said Nth sector from said non-volatile semiconductor memory into said controller,
carries out data processing for said Nth sector,
transmits said Nth sector after said data processing, to said host system via said system interface,
reads said (N+n)th sector from said non-volatile semiconductor memory for said data processing for said (N+n)th sector, while said controller transmits said Nth sector after said data processing to said host system via said system interface,
carries out said data processing for said (N+n)th sector, and
transmits said (N+n)th sector after said data processing, to said host system via said system interface.
12. A storage device as claimed in claim 11,
wherein said data processing is error correction processing of successive sectors.
13. A storage device as claimed in claim 10, comprising an error correction circuit for said successive sectors, and
wherein said controller starts transmitting said (N+n)th sector from said non-volatile semiconductor memory to said error correction circuit, while said controller transmits said Nth sector data having completed error correction processing by said error correction circuit, to said host system via said system interface.
14. A storage device as claimed in claim 10,
wherein said “n” is one.
15. A storage device as claimed in claim 10,
wherein a size of said sectors is 512 bytes.
16. A storage device as claimed in claim 10,
wherein said non-volatile semiconductor memory is a flash memory.
17. A storage device as claimed in claim 10,
wherein said non-volatile semiconductor memory is electrically erasable in a size of a sector data division.
18. A storage device, comprising:
a non-volatile semiconductor memory which is electrically erasable and which has first and second portions coupled to first and second data portions of a combination bus acting as first and second buses, respectively;
a system interface adapted to couple data and commands between the system interface and an external host system; and
a controller that reads data from the non-volatile semiconductor memory and transmits the data to the system interface in response to a read command received by the system interface;
wherein the controller starts reading second sector data from the non-volatile semiconductor memory via the second data portion of the combination bus as the second bus, while the controller transmits first sector data that has been read from the non-volatile semiconductor memory via the first data portion of the combination bus as the first bus to the system interface, in response to the read command.
19. A storage device as claimed in claim 18, wherein the controller, in response to the read command for successive sector data,
reads Nth sector data from the non-volatile semiconductor memory into the controller,
carries out data processing for the Nth sector data,
transmits the Nth sector data after the data processing to the system interface,
starts reading (N+n)th sector data from the non-volatile semiconductor memory for the data processing for the (N+n)th sector while the controller transmits the Nth sector data after the data processing to the system interface,
carries out the data processing for the (N+n)th sector data, and
transmits the (N+n)th sector data after the data processing to the system interface.
20. A storage device as claimed in claim 19,
wherein the data processing comprises error correction processing for the successive sector data.
21. A storage device as claimed in claim 19 comprising an error correction circuit for the successive sector data, and
wherein the controller starts transmitting said (N+n)th sector data from the non-volatile semiconductor memory to the error correction circuit, while the controller transmits error-corrected Nth sector data to the system interface.
22. A storage device as claimed in claim 19,
wherein “n” is one.
23. A storage device as claimed in claim 18,
wherein a size of the sector data is 512 bytes.
24. A storage device as claimed in claim 18,
wherein the non-volatile semiconductor memory comprises flash memory.
25. A storage device as claimed in claim 18,
wherein the non-volatile semiconductor memory is electrically erasable in a size of a sector unit.
26. A storage device as claimed in claim 18, wherein the first and second data portions are more particularly, upper and lower data portions, respectively, of the combination bus.
27. A storage device, comprising:
a non-volatile memory which is erasable and which has first and second portions coupled to first and second buses;
a system interface coupled with an external host system; and
a controller reading data from said non-volatile memory and transmitting said data to said host system via said system interface in response to a read command received by said system interface from said host system; and
wherein said controller starts reading (N+n)th addressable-subdivision data from said first portion of said non-volatile memory via said first bus, while said controller transmits Nth addressable-subdivision data that has been read from said second portion of said non-volatile memory via said second bus, to said host system via said system interface, in response to said read command for successive addressable-subdivision data, where N and n are integers.
US13475679 1995-07-14 2012-05-18 External storage device and memory access control method thereof Expired - Fee Related USRE45857E1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP17907595A JP3782840B2 (en) 1995-07-14 1995-07-14 External storage device and a memory access control method thereof
JP07-179075 1995-07-14
US08679960 US5732208A (en) 1995-07-14 1996-07-15 External storage device and memory access control method thereof
US4670598 true 1998-03-24 1998-03-24
US09544609 US6199187B1 (en) 1995-07-14 2000-04-06 External storage device and memory access control method thereof
US09750707 US6701471B2 (en) 1995-07-14 2001-01-02 External storage device and memory access control method thereof
US10748156 US7234087B2 (en) 1995-07-14 2003-12-31 External storage device and memory access control method thereof
US11599388 US7721165B2 (en) 1995-07-14 2006-11-15 External storage device and memory access control method thereof
US13475679 USRE45857E1 (en) 1995-07-14 2012-05-18 External storage device and memory access control method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13475679 USRE45857E1 (en) 1995-07-14 2012-05-18 External storage device and memory access control method thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11599388 Reissue US7721165B2 (en) 1995-07-14 2006-11-15 External storage device and memory access control method thereof

Publications (1)

Publication Number Publication Date
USRE45857E1 true USRE45857E1 (en) 2016-01-19

Family

ID=16059657

Family Applications (6)

Application Number Title Priority Date Filing Date
US08679960 Expired - Lifetime US5732208A (en) 1995-07-14 1996-07-15 External storage device and memory access control method thereof
US09544609 Expired - Lifetime US6199187B1 (en) 1995-07-14 2000-04-06 External storage device and memory access control method thereof
US09750707 Expired - Lifetime US6701471B2 (en) 1995-07-14 2001-01-02 External storage device and memory access control method thereof
US10748156 Expired - Lifetime US7234087B2 (en) 1995-07-14 2003-12-31 External storage device and memory access control method thereof
US11599388 Expired - Lifetime US7721165B2 (en) 1995-07-14 2006-11-15 External storage device and memory access control method thereof
US13475679 Expired - Fee Related USRE45857E1 (en) 1995-07-14 2012-05-18 External storage device and memory access control method thereof

Family Applications Before (5)

Application Number Title Priority Date Filing Date
US08679960 Expired - Lifetime US5732208A (en) 1995-07-14 1996-07-15 External storage device and memory access control method thereof
US09544609 Expired - Lifetime US6199187B1 (en) 1995-07-14 2000-04-06 External storage device and memory access control method thereof
US09750707 Expired - Lifetime US6701471B2 (en) 1995-07-14 2001-01-02 External storage device and memory access control method thereof
US10748156 Expired - Lifetime US7234087B2 (en) 1995-07-14 2003-12-31 External storage device and memory access control method thereof
US11599388 Expired - Lifetime US7721165B2 (en) 1995-07-14 2006-11-15 External storage device and memory access control method thereof

Country Status (3)

Country Link
US (6) US5732208A (en)
JP (1) JP3782840B2 (en)
KR (1) KR100227419B1 (en)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3782840B2 (en) * 1995-07-14 2006-06-07 株式会社ルネサステクノロジ External storage device and a memory access control method thereof
US6081878A (en) * 1997-03-31 2000-06-27 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
JP3614173B2 (en) 1996-02-29 2005-01-26 株式会社ルネサステクノロジ Semiconductor memory device with a partial defective memory
US5923682A (en) * 1997-01-29 1999-07-13 Micron Technology, Inc. Error correction chip for memory applications
US6275876B1 (en) * 1999-05-21 2001-08-14 International Business Machines Corporation Specifying wrap register for storing memory address to store completion status of instruction to external device
US6473872B1 (en) * 2000-03-08 2002-10-29 Infineon Technologies Ag Address decoding system and method for failure toleration in a memory bank
US6738942B1 (en) * 2000-06-02 2004-05-18 Vitesse Semiconductor Corporation Product code based forward error correction system
US7103821B2 (en) * 2002-07-03 2006-09-05 Intel Corporation Method and apparatus for improving network router line rate performance by an improved system for error checking
JP4368587B2 (en) * 2003-01-14 2009-11-18 富士通株式会社 Bus bridge circuit, bus connection system, and data error notification method of a bus bridge circuit
US20040193763A1 (en) * 2003-03-28 2004-09-30 Fujitsu Limited Inter-bus communication interface device and data security device
US7254747B2 (en) * 2003-03-28 2007-08-07 General Electric Company Complex system diagnostic service model selection method and apparatus
US6906961B2 (en) 2003-06-24 2005-06-14 Micron Technology, Inc. Erase block data splitting
EP1538525A1 (en) * 2003-12-04 2005-06-08 Texas Instruments France ECC computation simultaneously performed while reading or programming a flash memory
JP4357304B2 (en) * 2004-01-09 2009-11-04 株式会社バッファロー An external storage device
KR100626391B1 (en) * 2005-04-01 2006-09-13 삼성전자주식회사 Onenand flash memory and data processing system including the same
WO2008117111A3 (en) * 2006-10-04 2008-11-27 Marvell World Trade Ltd Flash memory control interface
US7797594B1 (en) * 2007-07-05 2010-09-14 Oracle America, Inc. Built-in self-test of 3-dimensional semiconductor memory arrays
KR101433620B1 (en) * 2007-08-17 2014-08-25 삼성전자주식회사 Decoder for increasing throughput using double buffering structure and pipelining technique and decoding method thereof
KR101466694B1 (en) * 2007-08-28 2014-11-28 삼성전자주식회사 ECC circuit, and storage device having the same, and method there-of
KR101437517B1 (en) * 2007-10-23 2014-09-05 삼성전자주식회사 Memory system using the interleaving scheme and method having the same
JP5218228B2 (en) * 2008-04-23 2013-06-26 新東工業株式会社 Conveying apparatus and the blasting machine
KR101510452B1 (en) * 2008-06-11 2015-04-10 삼성전자주식회사 The graphics memory data write control method and apparatus
JP5472808B2 (en) * 2010-03-01 2014-04-16 ソリッド ステート ストレージ ソリューションズ インク External storage device and a memory access control method thereof
US8799747B2 (en) * 2010-06-03 2014-08-05 Seagate Technology Llc Data hardening to compensate for loss of data retention characteristics in a non-volatile memory
US8713377B2 (en) 2011-12-15 2014-04-29 General Electric Company System and method to assess serviceability of device
KR20140055737A (en) 2012-11-01 2014-05-09 삼성전자주식회사 Memory module, memory system havint the same, and driving method thereof
US8959420B1 (en) * 2012-12-19 2015-02-17 Datadirect Networks, Inc. Data storage system and method for data migration between high-performance computing architectures and data storage devices using memory controller with embedded XOR capability
JP2015049633A (en) * 2013-08-30 2015-03-16 富士通株式会社 Information processing apparatus, data repair program, and data repair method
US9495242B2 (en) 2014-07-30 2016-11-15 International Business Machines Corporation Adaptive error correction in a memory system
US9772894B2 (en) * 2016-01-29 2017-09-26 Netapp, Inc. Systems, methods, and machine-readable media to perform state data collection
JP2018156716A (en) 2017-03-21 2018-10-04 株式会社東芝 Magnetic disk drive, the controller and method

Citations (126)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4064558A (en) 1976-10-22 1977-12-20 General Electric Company Method and apparatus for randomizing memory site usage
US4389715A (en) 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
US4498146A (en) 1982-07-30 1985-02-05 At&T Bell Laboratories Management of defects in storage media
JPS6236799Y2 (en) 1983-02-15 1987-09-18
JPS62239252A (en) 1986-04-09 1987-10-20 Nec Corp Storage device
JPS63219045A (en) 1987-03-09 1988-09-12 Hitachi Ltd Ic card
US4780855A (en) 1984-06-21 1988-10-25 Nec Corporation System for controlling a nonvolatile memory having a data portion and a corresponding indicator portion
JPS63200398U (en) 1987-06-11 1988-12-23
US4888773A (en) 1988-06-15 1989-12-19 International Business Machines Corporation Smart memory card architecture and interface
US4905242A (en) 1987-06-09 1990-02-27 The United States Of America As Represented By The Secretary Of The Air Force Pipelined error detection and correction apparatus with programmable address trap
JPH02123442A (en) 1988-11-02 1990-05-10 Hitachi Ltd Accelerated memory
JPH0224752Y2 (en) 1983-11-17 1990-07-06
US4949309A (en) 1988-05-11 1990-08-14 Catalyst Semiconductor, Inc. EEPROM utilizing single transistor per cell capable of both byte erase and flash erase
US4953122A (en) 1986-10-31 1990-08-28 Laserdrive Ltd. Pseudo-erasable and rewritable write-once optical disk memory system
US4970692A (en) 1987-09-01 1990-11-13 Waferscale Integration, Inc. Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin
JPH0262687B2 (en) 1986-12-25 1990-12-26 Suzuki Motor Co
US5021944A (en) 1988-07-08 1991-06-04 Hitachi, Ltd. Semiconductor memory having redundancy circuit for relieving defects
JPH03131951A (en) 1989-10-18 1991-06-05 Fujitsu Ltd Data transfer system
US5053990A (en) 1988-02-17 1991-10-01 Intel Corporation Program/erase selection for flash memory
US5058116A (en) 1989-09-19 1991-10-15 International Business Machines Corporation Pipelined error checking and correction for cache memories
US5067111A (en) 1988-10-28 1991-11-19 Kabushiki Kaisha Toshiba Semiconductor memory device having a majority logic for determining data to be read out
US5123016A (en) 1987-08-26 1992-06-16 Siemens Aktiengesellschaft Arrangement and method for identifying and localizing faulty circuits of a memory module
US5142540A (en) * 1990-03-13 1992-08-25 Glasser Lance A Multipart memory apparatus with error detection
JPH04308971A (en) 1991-04-06 1992-10-30 Nippon Steel Corp Binary search memory
JPH04311236A (en) 1991-04-09 1992-11-04 Nec Corp Memory error processing circuit
JPH04354218A (en) 1991-05-30 1992-12-08 Oki Electric Ind Co Ltd Data transmission system
US5172338A (en) 1989-04-13 1992-12-15 Sundisk Corporation Multi-state EEprom read and write circuits and techniques
US5198380A (en) 1988-06-08 1993-03-30 Sundisk Corporation Method of highly compact EPROM and flash EEPROM devices
US5200959A (en) 1989-10-17 1993-04-06 Sundisk Corporation Device and method for defect handling in semi-conductor memory
JPH0533252Y2 (en) 1986-11-14 1993-08-24
JPH0567005U (en) 1992-02-15 1993-09-03 九州電子株式会社 Lead frame for a semiconductor device
JPH05274219A (en) 1992-03-27 1993-10-22 Alps Electric Co Ltd Storage device
US5257367A (en) * 1987-06-02 1993-10-26 Cab-Tek, Inc. Data storage system with asynchronous host operating system communication link
US5267241A (en) * 1990-04-04 1993-11-30 Avasem Corporation Error correction code dynamic range control system
US5268319A (en) 1988-06-08 1993-12-07 Eliyahou Harari Highly compact EPROM and flash EEPROM devices
US5270979A (en) 1991-03-15 1993-12-14 Sundisk Corporation Method for optimum erasing of EEPROM
US5291584A (en) 1991-07-23 1994-03-01 Nexcom Technology, Inc. Methods and apparatus for hard disk emulation
US5293236A (en) 1991-01-11 1994-03-08 Fuji Photo Film Co., Ltd. Electronic still camera including an EEPROM memory card and having a continuous shoot mode
US5295255A (en) 1991-02-22 1994-03-15 Electronic Professional Services, Inc. Method and apparatus for programming a solid state processor with overleaved array memory modules
US5297029A (en) 1991-12-19 1994-03-22 Kabushiki Kaisha Toshiba Semiconductor memory device
US5297148A (en) 1989-04-13 1994-03-22 Sundisk Corporation Flash eeprom system
US5305282A (en) 1991-10-31 1994-04-19 Samsung Electric Co., Ltd. Address input buffer
JPH06110793A (en) 1992-09-30 1994-04-22 Toshiba Corp Monovolatile semiconductor memory
JPH06119128A (en) 1992-10-06 1994-04-28 Toshiba Corp Semiconductor disk device
EP0357361B1 (en) 1988-08-29 1994-05-04 Hitachi Maxell Ltd. IC card and method for writing information therein
JPH06124596A (en) 1991-11-28 1994-05-06 Hitachi Ltd Memory device using flash memory
US5315541A (en) 1992-07-24 1994-05-24 Sundisk Corporation Segmented column memory array
JPH0620483Y2 (en) 1986-08-26 1994-06-01 フクダ電子株式会社 Children, for premature infants living body leading electrode
US5335234A (en) 1990-06-19 1994-08-02 Dell Usa, L.P. Error correction code pipeline for interleaved memory system
US5341487A (en) 1991-12-20 1994-08-23 International Business Machines Corp. Personal computer having memory system with write-through cache and pipelined snoop cycles
EP0615184A2 (en) 1993-03-11 1994-09-14 International Business Machines Corporation Nonvolatile memory
US5361227A (en) 1991-12-19 1994-11-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and memory system using the same
EP0360526B1 (en) 1988-09-20 1994-11-23 Fujitsu Limited Semiconductor memory device having flash write function
US5396468A (en) 1991-03-15 1995-03-07 Sundisk Corporation Streamlined write operation for EEPROM system
US5422842A (en) 1993-07-08 1995-06-06 Sundisk Corporation Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells
JPH0756816B2 (en) 1987-09-30 1995-06-14 積水化学工業株式会社 Pipe fittings
US5428621A (en) 1992-09-21 1995-06-27 Sundisk Corporation Latent defect handling in EEPROM devices
US5430859A (en) 1991-07-26 1995-07-04 Sundisk Corporation Solid state memory system including plural memory chips and a serialized bus
JPH0744669Y2 (en) 1989-11-27 1995-10-11 株式会社淀川製鋼所 The connection structure of the heat insulating wall panel
US5459850A (en) 1993-02-19 1995-10-17 Conner Peripherals, Inc. Flash solid state drive that emulates a disk drive and stores variable length and fixed lenth data blocks
US5469558A (en) * 1991-08-16 1995-11-21 Multichip Technology Dynamically reconfigurable memory system with programmable controller and FIFO buffered data channels
US5471478A (en) 1991-09-13 1995-11-28 Sundisk Corporation Flash EEPROM array data and header file structure
US5473753A (en) 1992-10-30 1995-12-05 Intel Corporation Method of managing defects in flash disk memories
US5477495A (en) 1991-09-24 1995-12-19 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory apparatus
US5485474A (en) * 1988-02-25 1996-01-16 The President And Fellows Of Harvard College Scheme for information dispersal and reconstruction
US5491816A (en) * 1990-09-20 1996-02-13 Fujitsu Limited Input/ouput controller providing preventive maintenance information regarding a spare I/O unit
US5499337A (en) * 1991-09-27 1996-03-12 Emc Corporation Storage device array architecture with solid-state redundancy unit
US5504760A (en) 1991-03-15 1996-04-02 Sandisk Corporation Mixed data encoding EEPROM system
US5509018A (en) 1992-09-11 1996-04-16 International Business Machines Corporation Flash-erase-type nonvolatile semiconductor storage device
US5509134A (en) 1993-06-30 1996-04-16 Intel Corporation Method and apparatus for execution of operations in a flash memory array
US5508971A (en) 1994-10-17 1996-04-16 Sandisk Corporation Programmable power generation circuit for flash EEPROM memory systems
US5519843A (en) 1993-03-15 1996-05-21 M-Systems Flash memory system providing both BIOS and user storage capability
US5530828A (en) 1992-06-22 1996-06-25 Hitachi, Ltd. Semiconductor storage device including a controller for continuously writing data to and erasing data from a plurality of flash memories
US5532962A (en) 1992-05-20 1996-07-02 Sandisk Corporation Soft errors handling in EEPROM devices
US5537577A (en) 1992-05-11 1996-07-16 Matsushita Electric Industrial Co., Ltd. Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions
US5544356A (en) 1990-12-31 1996-08-06 Intel Corporation Block-erasable non-volatile semiconductor memory which tracks and stores the total number of write/erase cycles for each block
US5579502A (en) 1991-08-09 1996-11-26 Kabushiki Kaisha Toshiba Memory card apparatus using EEPROMS for storing data and an interface buffer for buffering data transfer between the EEPROMS and an external device
US5603001A (en) 1994-05-09 1997-02-11 Kabushiki Kaisha Toshiba Semiconductor disk system having a plurality of flash memories
US5612964A (en) * 1991-04-08 1997-03-18 Haraszti; Tegze P. High performance, fault tolerant orthogonal shuffle memory and method
US5630093A (en) 1990-12-31 1997-05-13 Intel Corporation Disk emulation for a non-volatile semiconductor memory utilizing a mapping table
US5629949A (en) * 1993-09-21 1997-05-13 Cirrus Logic, Inc. Error correction verification method and apparatus using CRC check remainders
US5640506A (en) 1995-02-15 1997-06-17 Mti Technology Corporation Integrity protection for parity calculation for raid parity cache
US5642316A (en) 1996-05-21 1997-06-24 Information Storage Devices, Inc. Method and apparatus of redundancy for non-volatile memory integrated circuits
US5644539A (en) 1991-11-26 1997-07-01 Hitachi, Ltd. Storage device employing a flash memory
US5649148A (en) 1992-10-08 1997-07-15 Mitel Corporation Fast digital signal processor interface using data interchanging between two memory banks
JPH09212429A (en) 1996-01-30 1997-08-15 Oki Electric Ind Co Ltd Monvolatile semiconductor disk drive
US5663901A (en) 1991-04-11 1997-09-02 Sandisk Corporation Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
WO1997032253A1 (en) * 1996-02-29 1997-09-04 Hitachi, Ltd. Semiconductor memory device having faulty cells
US5689727A (en) 1994-09-08 1997-11-18 Western Digital Corporation Disk drive with pipelined embedded ECC/EDC controller which provides parallel operand fetching and instruction execution
US5732208A (en) 1995-07-14 1998-03-24 Hitachi, Ltd. External storage device and memory access control method thereof
US5761220A (en) * 1994-09-19 1998-06-02 Cirrus Logic, Inc. Minimum latency asynchronous data path controller in a digital recording system
US5764571A (en) 1991-02-08 1998-06-09 Btg Usa Inc. Electrically alterable non-volatile memory with N-bits per cell
US5778418A (en) 1991-09-27 1998-07-07 Sandisk Corporation Mass computer storage system having both solid state and rotating disk types of memory
US5802551A (en) 1993-10-01 1998-09-01 Fujitsu Limited Method and apparatus for controlling the writing and erasing of information in a memory device
US5841712A (en) 1996-09-30 1998-11-24 Advanced Micro Devices, Inc. Dual comparator circuit and method for selecting between normal and redundant decode logic in a semiconductor memory device
US5845313A (en) 1995-07-31 1998-12-01 Lexar Direct logical block addressing flash memory mass storage architecture
US5859804A (en) 1991-10-16 1999-01-12 International Business Machines Corporation Method and apparatus for real time two dimensional redundancy allocation
US5878059A (en) * 1997-09-24 1999-03-02 Emc Corporation Method and apparatus for pipelining an error detection algorithm on an n-bit word stored in memory
US5889711A (en) 1997-10-27 1999-03-30 Macronix International Co., Ltd. Memory redundancy for high density memory
US5896327A (en) 1997-10-27 1999-04-20 Macronix International Co., Ltd. Memory redundancy circuit for high density memory with extra row and column for failed address storage
US5909541A (en) 1993-07-14 1999-06-01 Honeywell Inc. Error detection and correction for data stored across multiple byte-wide memory devices
US5909390A (en) 1988-06-08 1999-06-01 Harari; Eliyahou Techniques of programming and erasing an array of multi-state flash EEPROM cells including comparing the states of the cells to desired values
US5920515A (en) 1997-09-26 1999-07-06 Advanced Micro Devices, Inc. Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device
US5940335A (en) 1997-03-31 1999-08-17 International Business Machines Corporation Prioritizing the repair of faults in a semiconductor memory device
US5956524A (en) * 1990-04-06 1999-09-21 Micro Technology Inc. System and method for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources
US5995413A (en) 1998-01-09 1999-11-30 Information Storage Devices, Inc. Trimbit circuit for flash memory integrated circuits
US6002620A (en) 1998-01-09 1999-12-14 Information Storage Devices, Inc. Method and apparatus of column redundancy for non-volatile analog and multilevel memory
US6041368A (en) * 1997-04-02 2000-03-21 Matsushita Electric Industrial, Co. System for operating input, processing and output units in parallel and using DMA circuit for successively transferring data through the three units via an internal memory
US6058047A (en) 1996-08-16 2000-05-02 Tokyo Electron Limited Semiconductor memory device having error detection and correction
US6108253A (en) 1999-04-13 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Failure analysis system, fatal failure extraction method and recording medium
US6119245A (en) 1997-08-06 2000-09-12 Oki Electric Industry Co., Ltd. Semiconductor storage device and method of controlling it
US6125469A (en) * 1994-10-18 2000-09-26 Cirrus Logic, Inc. Error correction method and apparatus
US6145051A (en) 1995-07-31 2000-11-07 Lexar Media, Inc. Moving sectors within a block of information in a flash memory mass storage architecture
US6230233B1 (en) 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
US6347051B2 (en) * 1991-11-26 2002-02-12 Hitachi, Ltd. Storage device employing a flash memory
US6370059B2 (en) * 1992-07-06 2002-04-09 Hitachi, Ltd. Nonvolatile semiconductor memory
US6373758B1 (en) 2001-02-23 2002-04-16 Hewlett-Packard Company System and method of operating a programmable column fail counter for redundancy allocation
US6421279B1 (en) 1993-04-08 2002-07-16 Hitachi, Ltd. Flash memory control method and apparatus processing system therewith
US6426893B1 (en) 2000-02-17 2002-07-30 Sandisk Corporation Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US6445626B1 (en) 2001-03-29 2002-09-03 Ibm Corporation Column redundancy architecture system for an embedded DRAM
US6466478B1 (en) 2000-12-14 2002-10-15 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory device
US20030088611A1 (en) * 1994-01-19 2003-05-08 Mti Technology Corporation Systems and methods for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources
US6639857B2 (en) 2001-06-11 2003-10-28 Hynix Semiconductor Inc. Coding cell of nonvolatile ferroelectric memory device and operating method thereof, and column repair circuit of nonvolatile ferroelectric memory device having the coding cell and method for repairing column
US7289363B2 (en) 2005-05-19 2007-10-30 Micron Technology, Inc. Memory cell repair using fuse programming method in a flash memory device
US7617485B2 (en) * 2002-07-11 2009-11-10 Hitachi, Ltd. Apparatus for pointing an action attribute of electronic application system
US20140199461A1 (en) * 2004-08-12 2014-07-17 Sophie De Baets Functional sugar replacement

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567005A (en) 1991-09-09 1993-03-19 Nec Corp Recording medium access system
JPH0620483A (en) 1992-06-30 1994-01-28 Advanced Saakitsuto Technol:Kk Flash eeprom control circuit, and flash memory card
JPH0644144A (en) 1992-07-23 1994-02-18 Mitsubishi Electric Corp Semiconductor disk device
JPH06105443A (en) 1992-09-17 1994-04-15 Fujitsu Ltd Fluid carrier
GB9312199D0 (en) * 1993-06-14 1993-07-28 Raychem Gmbh Heat shrinkable article
JP2556655B2 (en) 1993-08-03 1996-11-20 東芝イーエムアイ株式会社 The data recording and reproducing apparatus
JPH0756816A (en) 1993-08-20 1995-03-03 Yokogawa Electric Corp Controller for memory

Patent Citations (156)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4064558A (en) 1976-10-22 1977-12-20 General Electric Company Method and apparatus for randomizing memory site usage
US4389715A (en) 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
US4498146A (en) 1982-07-30 1985-02-05 At&T Bell Laboratories Management of defects in storage media
JPS6236799Y2 (en) 1983-02-15 1987-09-18
JPH0224752Y2 (en) 1983-11-17 1990-07-06
US4780855A (en) 1984-06-21 1988-10-25 Nec Corporation System for controlling a nonvolatile memory having a data portion and a corresponding indicator portion
JPS62239252A (en) 1986-04-09 1987-10-20 Nec Corp Storage device
JPH0620483Y2 (en) 1986-08-26 1994-06-01 フクダ電子株式会社 Children, for premature infants living body leading electrode
US4953122A (en) 1986-10-31 1990-08-28 Laserdrive Ltd. Pseudo-erasable and rewritable write-once optical disk memory system
JPH0533252Y2 (en) 1986-11-14 1993-08-24
JPH0262687B2 (en) 1986-12-25 1990-12-26 Suzuki Motor Co
JPS63219045A (en) 1987-03-09 1988-09-12 Hitachi Ltd Ic card
US5257367A (en) * 1987-06-02 1993-10-26 Cab-Tek, Inc. Data storage system with asynchronous host operating system communication link
US4905242A (en) 1987-06-09 1990-02-27 The United States Of America As Represented By The Secretary Of The Air Force Pipelined error detection and correction apparatus with programmable address trap
JPS63200398U (en) 1987-06-11 1988-12-23
US5123016A (en) 1987-08-26 1992-06-16 Siemens Aktiengesellschaft Arrangement and method for identifying and localizing faulty circuits of a memory module
US4970692A (en) 1987-09-01 1990-11-13 Waferscale Integration, Inc. Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin
JPH0756816B2 (en) 1987-09-30 1995-06-14 積水化学工業株式会社 Pipe fittings
US5053990A (en) 1988-02-17 1991-10-01 Intel Corporation Program/erase selection for flash memory
US5485474A (en) * 1988-02-25 1996-01-16 The President And Fellows Of Harvard College Scheme for information dispersal and reconstruction
US4949309A (en) 1988-05-11 1990-08-14 Catalyst Semiconductor, Inc. EEPROM utilizing single transistor per cell capable of both byte erase and flash erase
US5198380A (en) 1988-06-08 1993-03-30 Sundisk Corporation Method of highly compact EPROM and flash EEPROM devices
US5268319A (en) 1988-06-08 1993-12-07 Eliyahou Harari Highly compact EPROM and flash EEPROM devices
US5909390A (en) 1988-06-08 1999-06-01 Harari; Eliyahou Techniques of programming and erasing an array of multi-state flash EEPROM cells including comparing the states of the cells to desired values
US4888773A (en) 1988-06-15 1989-12-19 International Business Machines Corporation Smart memory card architecture and interface
JPH06105443B2 (en) 1988-06-15 1994-12-21 インタ‐ナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Smart memory card
US5021944A (en) 1988-07-08 1991-06-04 Hitachi, Ltd. Semiconductor memory having redundancy circuit for relieving defects
EP0357361B1 (en) 1988-08-29 1994-05-04 Hitachi Maxell Ltd. IC card and method for writing information therein
EP0360526B1 (en) 1988-09-20 1994-11-23 Fujitsu Limited Semiconductor memory device having flash write function
US5067111A (en) 1988-10-28 1991-11-19 Kabushiki Kaisha Toshiba Semiconductor memory device having a majority logic for determining data to be read out
JPH02123442A (en) 1988-11-02 1990-05-10 Hitachi Ltd Accelerated memory
US5297148A (en) 1989-04-13 1994-03-22 Sundisk Corporation Flash eeprom system
US5719808A (en) 1989-04-13 1998-02-17 Sandisk Corporation Flash EEPROM system
US5172338A (en) 1989-04-13 1992-12-15 Sundisk Corporation Multi-state EEprom read and write circuits and techniques
US5418752A (en) 1989-04-13 1995-05-23 Sundisk Corporation Flash EEPROM system with erase sector select
US5172338B1 (en) 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
US5936971A (en) * 1989-04-13 1999-08-10 Sandisk Corporation Multi-state flash EEprom system with cache memory
US5058116A (en) 1989-09-19 1991-10-15 International Business Machines Corporation Pipelined error checking and correction for cache memories
US5200959A (en) 1989-10-17 1993-04-06 Sundisk Corporation Device and method for defect handling in semi-conductor memory
JPH03131951A (en) 1989-10-18 1991-06-05 Fujitsu Ltd Data transfer system
JPH0744669Y2 (en) 1989-11-27 1995-10-11 株式会社淀川製鋼所 The connection structure of the heat insulating wall panel
US5142540A (en) * 1990-03-13 1992-08-25 Glasser Lance A Multipart memory apparatus with error detection
US5267241A (en) * 1990-04-04 1993-11-30 Avasem Corporation Error correction code dynamic range control system
US5956524A (en) * 1990-04-06 1999-09-21 Micro Technology Inc. System and method for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources
US5335234A (en) 1990-06-19 1994-08-02 Dell Usa, L.P. Error correction code pipeline for interleaved memory system
US5491816A (en) * 1990-09-20 1996-02-13 Fujitsu Limited Input/ouput controller providing preventive maintenance information regarding a spare I/O unit
US5630093A (en) 1990-12-31 1997-05-13 Intel Corporation Disk emulation for a non-volatile semiconductor memory utilizing a mapping table
US5544356A (en) 1990-12-31 1996-08-06 Intel Corporation Block-erasable non-volatile semiconductor memory which tracks and stores the total number of write/erase cycles for each block
US5293236A (en) 1991-01-11 1994-03-08 Fuji Photo Film Co., Ltd. Electronic still camera including an EEPROM memory card and having a continuous shoot mode
US5764571A (en) 1991-02-08 1998-06-09 Btg Usa Inc. Electrically alterable non-volatile memory with N-bits per cell
US5295255A (en) 1991-02-22 1994-03-15 Electronic Professional Services, Inc. Method and apparatus for programming a solid state processor with overleaved array memory modules
US5396468A (en) 1991-03-15 1995-03-07 Sundisk Corporation Streamlined write operation for EEPROM system
US5270979A (en) 1991-03-15 1993-12-14 Sundisk Corporation Method for optimum erasing of EEPROM
US5504760A (en) 1991-03-15 1996-04-02 Sandisk Corporation Mixed data encoding EEPROM system
JPH04308971A (en) 1991-04-06 1992-10-30 Nippon Steel Corp Binary search memory
US5612964A (en) * 1991-04-08 1997-03-18 Haraszti; Tegze P. High performance, fault tolerant orthogonal shuffle memory and method
JPH04311236A (en) 1991-04-09 1992-11-04 Nec Corp Memory error processing circuit
US5663901A (en) 1991-04-11 1997-09-02 Sandisk Corporation Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
US6434034B1 (en) * 1991-04-11 2002-08-13 Sandisk Corporation Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
JPH04354218A (en) 1991-05-30 1992-12-08 Oki Electric Ind Co Ltd Data transmission system
US5291584A (en) 1991-07-23 1994-03-01 Nexcom Technology, Inc. Methods and apparatus for hard disk emulation
US5430859A (en) 1991-07-26 1995-07-04 Sundisk Corporation Solid state memory system including plural memory chips and a serialized bus
US5579502A (en) 1991-08-09 1996-11-26 Kabushiki Kaisha Toshiba Memory card apparatus using EEPROMS for storing data and an interface buffer for buffering data transfer between the EEPROMS and an external device
US5469558A (en) * 1991-08-16 1995-11-21 Multichip Technology Dynamically reconfigurable memory system with programmable controller and FIFO buffered data channels
US6230233B1 (en) 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
US5471478A (en) 1991-09-13 1995-11-28 Sundisk Corporation Flash EEPROM array data and header file structure
US5477495A (en) 1991-09-24 1995-12-19 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory apparatus
US5778418A (en) 1991-09-27 1998-07-07 Sandisk Corporation Mass computer storage system having both solid state and rotating disk types of memory
US5499337A (en) * 1991-09-27 1996-03-12 Emc Corporation Storage device array architecture with solid-state redundancy unit
US5859804A (en) 1991-10-16 1999-01-12 International Business Machines Corporation Method and apparatus for real time two dimensional redundancy allocation
US5305282A (en) 1991-10-31 1994-04-19 Samsung Electric Co., Ltd. Address input buffer
US6347051B2 (en) * 1991-11-26 2002-02-12 Hitachi, Ltd. Storage device employing a flash memory
US7327624B2 (en) * 1991-11-26 2008-02-05 Solid State Storage Solutions, Llc Storage device employing a flash memory
EP0548564B1 (en) 1991-11-26 1998-11-04 Hitachi, Ltd. Storage device employing a flash memory
US6567334B2 (en) * 1991-11-26 2003-05-20 Hitachi, Ltd. Storage device employing a flash memory
US5644539A (en) 1991-11-26 1997-07-01 Hitachi, Ltd. Storage device employing a flash memory
US7064995B2 (en) * 1991-11-26 2006-06-20 Renesas Technology Corp. Storage device employing a flash memory
JPH06124596A (en) 1991-11-28 1994-05-06 Hitachi Ltd Memory device using flash memory
US5361227A (en) 1991-12-19 1994-11-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and memory system using the same
US5297029A (en) 1991-12-19 1994-03-22 Kabushiki Kaisha Toshiba Semiconductor memory device
US5341487A (en) 1991-12-20 1994-08-23 International Business Machines Corp. Personal computer having memory system with write-through cache and pipelined snoop cycles
JPH0567005U (en) 1992-02-15 1993-09-03 九州電子株式会社 Lead frame for a semiconductor device
JPH05274219A (en) 1992-03-27 1993-10-22 Alps Electric Co Ltd Storage device
US5537577A (en) 1992-05-11 1996-07-16 Matsushita Electric Industrial Co., Ltd. Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions
US5532962A (en) 1992-05-20 1996-07-02 Sandisk Corporation Soft errors handling in EEPROM devices
US5530828A (en) 1992-06-22 1996-06-25 Hitachi, Ltd. Semiconductor storage device including a controller for continuously writing data to and erasing data from a plurality of flash memories
US7746697B2 (en) * 1992-07-06 2010-06-29 Solid State Storage Solutions, Inc. Nonvolatile semiconductor memory
US6370059B2 (en) * 1992-07-06 2002-04-09 Hitachi, Ltd. Nonvolatile semiconductor memory
US7366016B2 (en) * 1992-07-06 2008-04-29 Solid State Storage Solutions, Llc Nonvolatile semiconductor memory
US5315541A (en) 1992-07-24 1994-05-24 Sundisk Corporation Segmented column memory array
US5509018A (en) 1992-09-11 1996-04-16 International Business Machines Corporation Flash-erase-type nonvolatile semiconductor storage device
US5844910A (en) 1992-09-11 1998-12-01 International Business Machines Corporation Flash-erase-type nonvolatile semiconductor storage device
US5428621A (en) 1992-09-21 1995-06-27 Sundisk Corporation Latent defect handling in EEPROM devices
JPH06110793A (en) 1992-09-30 1994-04-22 Toshiba Corp Monovolatile semiconductor memory
JPH06119128A (en) 1992-10-06 1994-04-28 Toshiba Corp Semiconductor disk device
US5572466A (en) 1992-10-06 1996-11-05 Kabushiki Kaisha Toshiba Flash memory chips
US5649148A (en) 1992-10-08 1997-07-15 Mitel Corporation Fast digital signal processor interface using data interchanging between two memory banks
US5473753A (en) 1992-10-30 1995-12-05 Intel Corporation Method of managing defects in flash disk memories
US5459850A (en) 1993-02-19 1995-10-17 Conner Peripherals, Inc. Flash solid state drive that emulates a disk drive and stores variable length and fixed lenth data blocks
US5734816A (en) 1993-03-11 1998-03-31 International Business Machines Corporation Nonvolatile memory with flash erase capability
EP0615184A2 (en) 1993-03-11 1994-09-14 International Business Machines Corporation Nonvolatile memory
US5519843A (en) 1993-03-15 1996-05-21 M-Systems Flash memory system providing both BIOS and user storage capability
US6421279B1 (en) 1993-04-08 2002-07-16 Hitachi, Ltd. Flash memory control method and apparatus processing system therewith
US5509134A (en) 1993-06-30 1996-04-16 Intel Corporation Method and apparatus for execution of operations in a flash memory array
US5422842A (en) 1993-07-08 1995-06-06 Sundisk Corporation Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells
US5909541A (en) 1993-07-14 1999-06-01 Honeywell Inc. Error detection and correction for data stored across multiple byte-wide memory devices
US5629949A (en) * 1993-09-21 1997-05-13 Cirrus Logic, Inc. Error correction verification method and apparatus using CRC check remainders
US5802551A (en) 1993-10-01 1998-09-01 Fujitsu Limited Method and apparatus for controlling the writing and erasing of information in a memory device
US6766409B2 (en) 1993-10-01 2004-07-20 Fujitsu Limited Method of writing, erasing, and controlling memory for memory device
US20030088611A1 (en) * 1994-01-19 2003-05-08 Mti Technology Corporation Systems and methods for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources
US5603001A (en) 1994-05-09 1997-02-11 Kabushiki Kaisha Toshiba Semiconductor disk system having a plurality of flash memories
US5689727A (en) 1994-09-08 1997-11-18 Western Digital Corporation Disk drive with pipelined embedded ECC/EDC controller which provides parallel operand fetching and instruction execution
US5761220A (en) * 1994-09-19 1998-06-02 Cirrus Logic, Inc. Minimum latency asynchronous data path controller in a digital recording system
US5508971A (en) 1994-10-17 1996-04-16 Sandisk Corporation Programmable power generation circuit for flash EEPROM memory systems
US6125469A (en) * 1994-10-18 2000-09-26 Cirrus Logic, Inc. Error correction method and apparatus
US5640506A (en) 1995-02-15 1997-06-17 Mti Technology Corporation Integrity protection for parity calculation for raid parity cache
US5732208A (en) 1995-07-14 1998-03-24 Hitachi, Ltd. External storage device and memory access control method thereof
US6701471B2 (en) 1995-07-14 2004-03-02 Hitachi, Ltd. External storage device and memory access control method thereof
US5845313A (en) 1995-07-31 1998-12-01 Lexar Direct logical block addressing flash memory mass storage architecture
US6115785A (en) 1995-07-31 2000-09-05 Lexar Media, Inc. Direct logical block addressing flash memory mass storage architecture
US6145051A (en) 1995-07-31 2000-11-07 Lexar Media, Inc. Moving sectors within a block of information in a flash memory mass storage architecture
JPH09212429A (en) 1996-01-30 1997-08-15 Oki Electric Ind Co Ltd Monvolatile semiconductor disk drive
US7616485B2 (en) 1996-02-29 2009-11-10 Solid State Storage Solutions Llc Semiconductor memory device having faulty cells
JP4563465B2 (en) 1996-02-29 2010-10-13 ソリッド ステート ストレージ ソリューションズ エルエルシー Nonvolatile semiconductor memory device
US20040022249A1 (en) 1996-02-29 2004-02-05 Kunihiro Katayama Semiconductor memory device having faulty cells
WO1997032253A1 (en) * 1996-02-29 1997-09-04 Hitachi, Ltd. Semiconductor memory device having faulty cells
US6236601B1 (en) 1996-02-29 2001-05-22 Hitachi, Ltd. Semiconductor memory device having faulty cells
US6317371B2 (en) 1996-02-29 2001-11-13 Hitachi, Ltd. Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory
US8064257B2 (en) 1996-02-29 2011-11-22 Solid State Storage Solutions, Inc. Semiconductor memory device having faulty cells
US6728138B2 (en) 1996-02-29 2004-04-27 Renesas Technology Corp. Semiconductor memory device having faulty cells
US6542405B2 (en) 1996-02-29 2003-04-01 Hitachi, Ltd. Semiconductor memory device having faulty cells
US6388920B2 (en) 1996-02-29 2002-05-14 Hitachi, Ltd. Semiconductor memory device having faulty cells
US6031758A (en) 1996-02-29 2000-02-29 Hitachi, Ltd. Semiconductor memory device having faulty cells
US5642316A (en) 1996-05-21 1997-06-24 Information Storage Devices, Inc. Method and apparatus of redundancy for non-volatile memory integrated circuits
US6058047A (en) 1996-08-16 2000-05-02 Tokyo Electron Limited Semiconductor memory device having error detection and correction
JP2001501000A (en) 1996-08-16 2001-01-23 東京エレクトロン株式会社 Error detection and semiconductor memory device having a correction
US5841712A (en) 1996-09-30 1998-11-24 Advanced Micro Devices, Inc. Dual comparator circuit and method for selecting between normal and redundant decode logic in a semiconductor memory device
US5940335A (en) 1997-03-31 1999-08-17 International Business Machines Corporation Prioritizing the repair of faults in a semiconductor memory device
US6041368A (en) * 1997-04-02 2000-03-21 Matsushita Electric Industrial, Co. System for operating input, processing and output units in parallel and using DMA circuit for successively transferring data through the three units via an internal memory
US6119245A (en) 1997-08-06 2000-09-12 Oki Electric Industry Co., Ltd. Semiconductor storage device and method of controlling it
US5878059A (en) * 1997-09-24 1999-03-02 Emc Corporation Method and apparatus for pipelining an error detection algorithm on an n-bit word stored in memory
US5920515A (en) 1997-09-26 1999-07-06 Advanced Micro Devices, Inc. Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device
US5896327A (en) 1997-10-27 1999-04-20 Macronix International Co., Ltd. Memory redundancy circuit for high density memory with extra row and column for failed address storage
US5889711A (en) 1997-10-27 1999-03-30 Macronix International Co., Ltd. Memory redundancy for high density memory
US5995413A (en) 1998-01-09 1999-11-30 Information Storage Devices, Inc. Trimbit circuit for flash memory integrated circuits
US6002620A (en) 1998-01-09 1999-12-14 Information Storage Devices, Inc. Method and apparatus of column redundancy for non-volatile analog and multilevel memory
US6108253A (en) 1999-04-13 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Failure analysis system, fatal failure extraction method and recording medium
US6426893B1 (en) 2000-02-17 2002-07-30 Sandisk Corporation Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US7002844B2 (en) 2000-12-14 2006-02-21 Samsung Electronics Co., Ltd. Method of repairing a failed wordline
US6466478B1 (en) 2000-12-14 2002-10-15 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory device
US6373758B1 (en) 2001-02-23 2002-04-16 Hewlett-Packard Company System and method of operating a programmable column fail counter for redundancy allocation
US6445626B1 (en) 2001-03-29 2002-09-03 Ibm Corporation Column redundancy architecture system for an embedded DRAM
US6639857B2 (en) 2001-06-11 2003-10-28 Hynix Semiconductor Inc. Coding cell of nonvolatile ferroelectric memory device and operating method thereof, and column repair circuit of nonvolatile ferroelectric memory device having the coding cell and method for repairing column
US7617485B2 (en) * 2002-07-11 2009-11-10 Hitachi, Ltd. Apparatus for pointing an action attribute of electronic application system
US20140199461A1 (en) * 2004-08-12 2014-07-17 Sophie De Baets Functional sugar replacement
US7289363B2 (en) 2005-05-19 2007-10-30 Micron Technology, Inc. Memory cell repair using fuse programming method in a flash memory device

Non-Patent Citations (20)

* Cited by examiner, † Cited by third party
Title
Curt Fritze, News Release, Revolutionary High Performance, High Capacity Romdisk Solid-State Disk and Derive Emulator, Jan. 15, 1991.
Defendants' Invalidity Contentions memo (including Exhibits B and F1-F12), in Eastern District of Texas, Case No. 2:11-CV-391-JRG (Aug. 3, 2012).
Ehibit C-Motivation to Combine References.
Ehibit D-Motivation to Combine References.
Ehibits E-1 Thru E-27.
Ehibits G-1 Thru G-21.
Ehibits H-1 Thru H-10.
Exhibit A-Motivation to Combine References.
HN58064 Series, 8192-word×8-bit Electrically Erasable and Programmable ROM, (6 pgs.).
HN58064P-25, HN58064P-30, HN58064P-45 Preliminary 8192-word×8-bit Electrically Erasable and Programmable ROM, (5 pgs.).
Iwata, et al., A High-Density NAND EEPROM with Block-Page Programming for Microcomputer Applications, IEEE Journal of Solid-State Circuits, vol. 25, No. 2, Apr. 1990, pp. 417-424.
John Reimer, Fujitsu Microelectronics, Inc., PC Card Standard Release 1.0, Personal Computer Memory Card International Association, Nov. 1990.
Keith Fritze, Programming Interface Specification, Feb. 24, 1992, pp. 1-13.
Kynett, et al., An In-System Reprogrammable 32K×8 CMOS Flash Memory, IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1157-1163.
Lahti, W. et al: "Store Data in a Flash", BYTE, Nov. 1990, pp. 311-313, 315 and 317.
Markus Levy, Interfacing Microsoft's Flash File System, Reprinted with permission from Circuit Cellar, Inc., Jun./Jul. 1991, pp. 4-318-4-325.
Momodomi, et al: "A 4-Mb NAND EEPROM with Tight Programmed Vt, Distribution," IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 492-496.
Niijima, et al, "Design of a Solid-State File Using Flash EEPROM" (IBM J. Res. Develop., vol. 39, No. 5, Sep. 1995, pp. 531-543.
Pashley, R. et al: "Flash Memories: the Best of Two Worlds," IEEE Spectrum, vol. 26, No. 12, Dec. 1989, pp. 4-6 and 30-33.
Wszola, S., et al: "Review Flashdisk: Not Your Father's RAM Disk", BYTE, Sep. 1990, pp. 214-215.

Also Published As

Publication number Publication date Type
US20040172581A1 (en) 2004-09-02 application
JPH0934740A (en) 1997-02-07 application
US7721165B2 (en) 2010-05-18 grant
JP3782840B2 (en) 2006-06-07 grant
KR100227419B1 (en) 1999-11-01 grant
US20010001327A1 (en) 2001-05-17 application
US5732208A (en) 1998-03-24 grant
US6701471B2 (en) 2004-03-02 grant
US20070168782A1 (en) 2007-07-19 application
US7234087B2 (en) 2007-06-19 grant
US6199187B1 (en) 2001-03-06 grant

Similar Documents

Publication Publication Date Title
US5822251A (en) Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers
US7111142B2 (en) System for quickly transferring data
US5381538A (en) DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
US5185876A (en) Buffering system for dynamically providing data to multiple storage elements
US6151641A (en) DMA controller of a RAID storage controller with integrated XOR parity computation capability adapted to compute parity in parallel with the transfer of data segments
US5283877A (en) Single in-line DRAM memory module including a memory controller and cross bar switches
US6236593B1 (en) Method for simultaneously programming plural flash memories having invalid blocks
US5408627A (en) Configurable multiport memory interface
US5511210A (en) Vector processing device using address data and mask information to generate signal that indicates which addresses are to be accessed from the main memory
US6034891A (en) Multi-state flash memory defect management
US4757440A (en) Pipelined data stack with access through-checking
US5390149A (en) System including a data processor, a synchronous dram, a peripheral device, and a system clock
US6408356B1 (en) Apparatus and method for modifying signals from a CPU to a memory card
US5675726A (en) Flexible parity generation circuit
US4658349A (en) Direct memory access control circuit and data processing system using said circuit
US5373512A (en) Memory controller with parity generator for an I/O control unit
US5267241A (en) Error correction code dynamic range control system
US5623620A (en) Special test modes for a page buffer shared resource in a memory device
US6493789B2 (en) Memory device which receives write masking and automatic precharge information
US5648929A (en) Flash memory card
US6859856B2 (en) Method and system for a compact flash memory controller
US5844855A (en) Method and apparatus for writing to memory components
US5778412A (en) Method and apparatus for interfacing a data bus to a plurality of memory devices
US4600986A (en) Pipelined split stack with high performance interleaved decode
US4394753A (en) Integrated memory module having selectable operating functions

Legal Events

Date Code Title Description
AS Assignment

Owner name: ACACIA RESEARCH GROUP LLC, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SOLID STATE STORAGE SOLUTIONS, INC.;REEL/FRAME:040886/0619

Effective date: 20151228

AS Assignment

Owner name: EMERGENCE MEMORY SOLUTIONS LLC, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ACACIA RESEARCH GROUP LLC;REEL/FRAME:041176/0010

Effective date: 20161212

FEPP

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.)