JPS63219045A - Ic card - Google Patents

Abstract

PURPOSE:To rewrite a data a number of times more than the life of an EEPROM itself by finding out an area, in which the reliability of a held data decreases in the EEPROM, and securing and using a preparatory storage area substituting for it. CONSTITUTION:The area of the EEPROM (electrically erasable and writable non-volatile memory) 15 is divided into an open area, an operation area, a secret area and a preparatory area. The preparatory area is the area that the substituting storage area of a defective address whose reliability is decided to be decreased in the operation area, is secured. A correspondence relation between the defective address and its substituting address is held in a PROM 16 as a defective address map. When a data on the operation area is read out, at first, it is checked whether it is the defective address or not, by referring to the defective address map in the PROM 16, and if it is registered as the defective address, the substituting address comes to be the candidate of the address, in which the data to be read out next time is held.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an IC in which an IC chip is attached to a plastic plate.
The present invention relates to an IC card suitable for use in which data to be stored is frequently replaced.

[Conventional technology]

Conventional IC cards that allow rewritable data are those that have an IC chip attached to a plastic plate, as discussed in Science, January 1986, pages 84 to 93. There are three types of memory: ROM (read-only memory) for program storage, RAM (volatile memory that can be read and written) for temporary data storage, and EEPROM (electrically erasable and programmable ROM) for data storage. A CPU and an input/output device were installed to control all signal exchange with external devices outside the card, resulting in an 'fc configuration.

[Problem that the invention seeks to solve]

In the above conventional technology, EEP is used to store data.
ROM (Electrically Erasable and Programmable Non-Volatile Memory) is used, but EEPROM is not infinitely reprogrammable. EEPR
Due to the presence of defects in the thin insulating layer of silicon dioxide that makes up the OM, after 10,000 reprograms from 0 to 1.1 to 0, the silicon dioxide layer has a significant amount of '1. The child is trapped and a leakage path is formed, resulting in a constant low flow (ie, always 00). Therefore, in areas in the EEPROM where data is frequently rewritten, a problem arises in that the reliability of the data held gradually decreases.

A first object of the present invention is to provide an IC card that prevents the reliability of data in the EEPROM from decreasing.

A second object of the present invention is to detect a decrease in data reliability (malfunction) in the EEPROM and correct the error.
The purpose is to provide C cards.

[Means for solving problems]

In order to achieve the above object, the first feature of the invention is to provide a spare area in the EEPBOM in the above-mentioned IC chip, and furthermore, to provide a memory address in a regular area in the EEPROM where the reliability of data retention is lowered. and the alternative address secured in the above-mentioned spare area (hereinafter referred to as a defective address map).

) is to provide a memory for storing the information. This memory is 280M (non-volatile memory that can be written once)
Or EEPkLOM. The ROM that stores the program that describes all the operations of the IC contains the FR
After address conversion is performed using the defective address map recorded in the OM, a program is stored that has an added function of reading and writing to the appropriate address on the EEPROM.

In addition, in order to achieve the above object, the second feature of the present invention is that in addition to the EEPROM for data storage on the IC chip, data is stored with a structure equal to the first EEPR and OM with positive and negative logic. A second EEPROM is provided, and the contents of the same address 1 of these two EEPROMs are read out and compared. Alternatively, means for writing data to the same memory address may be provided.

[Effect]

The first feature is that when reading data sound at a certain address i (in a commonly used area) in the EEL' OM, the PROM
Refer to the defective address map in If i is not recorded in the defective address map, the reliability of the data held at address 1 is high.L EEPROM address! Read out the contents of 11. If i is recorded in the defective address map, the alternative address j (EEP
(in the spare area of the ROM) is a candidate address where data to be read next is held. This j is also checked to see if it is recorded in the defective address map, and if so, an alternative address k for J is selected as a candidate for the read address. The above operations are repeated until finally a candidate t for an address not recorded in the defective address map is obtained. And the address L (
Of course, the contents of the spare area) are read out and stored at address i.
This is the result of reading the contents of .

Next, it is necessary to write data to a certain address i (in the common area) in the EEPROM, but first, by the same operation as in the case of reading, an address @J (this is written to i) that is not recorded in the defective strip map is (It may be the same address, or it may be an address in another spare area.) and write data to this address j. Next, read the contents of j,
Check whether the data was recorded correctly. If the check results are correct, this is the end. If it is not recorded correctly, J is recorded in the defective address map, and at the same time, an unused address k in the spare area is found and k is also recorded. The data is then written to address k, and then read out to check the contents. By repeating these steps until the check results are correct, the reliability decreases (
It is possible to prevent data from being written to a memory address (which increases the possibility of malfunction).

Note that here, the defective address map is the EE that holds the data.
It is assumed that it is held in 280M separate from PROM, but
There is no problem even if it is realized as a defective address map area in the same way as a spare area in the EEPROM.

This is because the reliability of this recording itself is high, since the defective address map is information that is never changed once it is recorded.

Moreover, in the second feature, in the IC chip.

When writing data, write the data to be stored in the 10th E.
Write to a specified address in EP R, 0M, and also write this data with reverse logic (that is, take negation)
Write to the relatively same address in the second EEPROM.

In EEPROM, if data is updated frequently, the reliability of data retention decreases (causing malfunction).
For example, a bit that has malfunctioned will always be in a 0 state. In other words, the probability that 1 becomes 0 by mistake increases. Compared to this, the probability that 0 becomes 1 by mistake is extremely low. 0 again
There is no problem with remembering the key.

The first EEPROM and the second EEPROM store data in a reverse 0, 1 pattern at corresponding memory addresses, but each EEPROM malfunctions in the following six cases. is possible. Each gEpfL
Let the corresponding bits in oM be A and B.

(1) A: 1→ 0 (2) A: 0→ 1 (3) B: 1-→ 0 (4) B: 0→ 1 (5) A; 1→ 0. B: 0 → 1 (6)
A: O→ 1. B: 1 → O However, case (ノ,
In cases (4), (5), and (6), malfunction from 0 to 1 is extremely unlikely to occur, so the probability that cases (1) and (3) will occur is much higher than in these cases. In (L) and (3), both A and B are likely to be 0 as a result. When reading the stored data, the contents of each predetermined address of the first EEPROM and the second EEPROM are read, and the corresponding bits of the two data are compared. If all bits are inverted with respect to each other (this can be seen by taking the exclusive logical interest between corresponding bits), it can be determined that all data is correctly held, so the first The data read from the EEPROM may be used as is.

Conversely, as a result of the comparison, a certain bit A corresponding to the two data
%A if both and B are 0.

Either B malfunctions (cases (1) or (3)), but it is determined that either (1) or (3) is not working.

Therefore, correct the data by following the steps below.
, writes 1 to B and reads it. Based on the results, malfunctions can be classified into the following three patterns.

(b) A: 0. B: 1 (Only A malfunctions) (B) A:
1, B: 0 (only B malfunctions)? i A: 0
, a2o (If both A and B malfunction (b), it can be determined as case (1), so A can be corrected to 1. Also, in the case of (r: IJ, it can be determined as case (3), so It turns out that A can be left as 0. Since both A and B are malfunctioning in rt, it is not possible to determine whether it is case (1) or case (3), and it is impossible to determine whether A is O or 1. Although it is not possible, this probability is considered to be low compared to the probability of (a) -? ((b).

As described above, the first EEPROM and the second EEPROM
If one of the corresponding storage areas malfunctions,
Malfunctions can be detected and data read from the tenth EEPROM can be corrected.

Note that the first read data is returned to A and B.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the device configuration of an embodiment of an IC chip in an IC card. In the figure, reference numeral 11 denotes a CPU, which controls all data exchange between the memory within the chip and various external devices outside the card. Reference numeral 12 designates an input/output device that actually inputs and outputs data. Reference numeral 13 denotes a ROM (read-only non-volatile memory), which stores a group of instructions (program) that the CPU II should follow when given a certain instruction from the outside. 14 is a RAM (readable/writable volatile memory) which is a work area when the CPU operates. And 15 is EEPROIld (electrically erasable and writable non-volatile memory) in which data is actually recorded. 16 is a 280M (one-time writable nonvolatile memory) in which a defective address map regarding the EEPROM 15 described above is recorded.

FIG. 2 shows an example in which the inside of the EEPROM 15 for data recording is divided into four types of areas depending on the purpose of data use. Each is an open area 21. Operating area 22. Secret area 23. This will be called a spare area 24. open area 21
The IC card holder's name, address, account number, etc. are recorded in the area, and the contents of this area can be read by any card reader.

Rewriting is carried out either by software or by a node using a program stored in the 0M13. The operation area 22 is used, for example, to record the amount, date, etc. when using the card for shopping. The CPU II is only allowed to write and read this area under certain conditions (for example, if the card's PIN number has been entered correctly). The secret area 23 contains the card's PIN number! This area stores the code of the R manufacturing company and is inaccessible to the cardholder. Of the three areas mentioned above, the operation area 22, whose contents can be repeatedly rewritten, may have lower reliability of the data it holds than the other two areas. The spare area 24 is a storage area reserved as an alternative storage area for a storage address (hereinafter referred to as a defective address) whose reliability has been determined to have deteriorated in the operation area 22.

The correspondence relationship between a defective address i and its alternative address (referred to as m (i)) (hereinafter referred to as a defective address map) is FROM
It is held at 16. FIG. 3 is an example of a representation of a defective address map in a PROM. In the figure, 30 is the address on 280M, 3
1 indicates a column for defective address 1, and 32 indicates a column for alternative address m(i).

Next, the procedure for reading data at address l on the operating area 22 in the EEPROM 15 will be explained using the flowchart of FIG. 4(a). First, the defective address map in PROMIa is referred to. It is checked whether address i is recorded in the defective address field 31 in the map (step 42).

If i is not recorded, the contents of address i are read (step 44). When an address i is recorded in the defective address column 31, the corresponding address m(+) in the alternative address column 32 is a candidate address where data to be read next is held.

Let this m(1)' be i again (step 43)
.

It is checked whether this i is also recorded in the failed address field 31 of the defective address map (step 42), and if it is recorded, the alternative address m(i) for 1 is selected as a candidate for the address to be read next (step 43). The above operations (steps 42 and 43) are repeated until a recording address candidate is finally obtained for the defective address vlA31.Then, the obtained address i
(of course in the spare area 24) and make this the content of the address on the first given operating area 22 (
Step 44).

Next, the procedure for writing data into the operating area 220 address 1 in the EEPROM 15 will be explained using the flowchart shown in FIG. 4(b). First, the same operation as in the case of data reading is performed, and a candidate address (hereafter referred to as i) that is not recorded in the defective address column 31 is used. It may be another address in 24. Find it (steps 46 and 47). Then, write data into this address (step 48). Next, read the existence of this address (step 49), and check if the data is correct. Check whether it has been recorded (step 50). If it is not recorded correctly,
1 is registered in the defective address column 31 of the defective address map, and at the same time, an unused memory address m(j) in the spare area 24 is found and recorded in the alternative address column 32 (step 51). This m) is newly set to 1 (step 51). And data 'f1:g! at this address i! Input (step 48),
Subsequently, reading is performed and the contents are compared (step 49).
．． 50).

By repeating this operation (steps 48 to 51) until the comparison result is correct, data is stored in the spare area 24 as an alternative storage area for the operating area 22.

According to this embodiment, a defective memory address whose data retention reliability has deteriorated due to frequent replacement in the operating area 22 and spare area 241c in the EEPR (JM 15) is discovered, and the defective memory address is removed. EEPR the alternate memory address
Since the memory address is secured in a spare area within the OM and this alternative storage address is used thereafter, there is an advantage that data can be rewritten for a period longer than the life of the EEPROM.

In addition, in this embodiment, FR is used as a storage area for the defective address map in addition to the data storage area EEPR, OM 15.
Although the configuration includes the OM (one-time writeable ROM) 16, it is also possible to provide a defective address map area as the fifth area in the EEPROM 15.

FIG. 5 shows the device configuration of another embodiment within the IC chip within the IC card. In the figure, 61 is a CPU that controls all data exchange between the memory in the chip and various external devices outside the card. 62 is an input/output device that actually inputs and outputs data. 63 is a ROM (read-only non-volatile memory), which stores a group of instructions (program) to be prompted when the CPU 61 is given a certain instruction from the outside. 64 is a RAM (readable/writable volatile memory), which is a work area when the CPU 61 operates. And 65 is an EEPROM ('II, a non-volatile memory that is erasable and programmable), in which data is actually recorded (this will be called EEPROMl). j066 is the EEPROM of 65. (This will be referred to as f:EEPROM2), and the same data is recorded in the relatively same address as EEPROM1 with opposite logic.And 67 is EEPROM1 of 65 and EEPROM1 of 66 This is a comparator circuit that performs convolutional reading of data regarding the same location of the EEPROM 2 and performs data error correction using the two read data, and operates under the control of the CPU 61.

When the CPU 61 writes data to the address i in the EEPROM1, the comparison circuit 67 receives the address i and the data from the CPU 61, writes the data to the address i in the EEPROM PMI, and simultaneously inverts 1 and 0 of each bit of this data. The resulting data is written to address i of EEPROM2.

When the CPU 61 reads data at address 1 in the EEPROM1, the comparator circuit 67 receives address 1 from the CPU 61 and 9. Data a and data b are read from each of seven addresses i in EEPROM1 and EEPROM2. The comparator circuit 67 performs an exclusive sum between a and b for each bit. If the result is all 1 (0 and 1 are inverted with each other in all bits), leave data a as 7 and write E.
It is sent to the CPU 61 as the contents of address i of EPROMI.

If there is a bit that is 0 in both a and b (this position is K), then the data a obtained by negating a and b
, l)l EEPROMI and EEPRO respectively
The data is stored in address l of M2, and then the contents of address i are read out. Let these be c and d. between a and C, and b and d
Exclusive OR is performed for every n bits between them. The values at the bit positions in each result are set as e and f, and the following processing is performed depending on the values of e and f.

(b) e=1. If f=0, it is determined that only the EEPROMI has malfunctioned, and the data a is corrected to P/Kil.

(b) e=0. When f=1, K EEPfLOM
2(7), it is determined that the ME is malfunctioning. data a
There is no need to correct the bits in .

(c) In the case of e=f=l, two OEEPR, OM
It is determined that a malfunction has occurred in the CPU 11, and the CPU 11 is notified that the data cannot be read, and the process is stopped.

Above (a), (n' is performed for all pit positions K where malfunctions were detected, and the corrected data 'eE
It is sent to the CPU 61 as the EPROM address io contents.

Finally, set a and b to the original address i of each EEPROM.
I'll put it back.

As described above, according to the present embodiment, by reading and comparing the contents of EEPROM1 and EEPROM2, it is possible to detect whether or not a data retention malfunction has occurred in each EEPROM, and to correct it. This has the effect of improving retention reliability.

〔Effect of the invention〕

As described above, according to the present invention, the E
By discovering an area in the EPRPM where the reliability of retained data has deteriorated (caused a malfunction) due to frequent rewriting, securing a spare storage area to replace it, and using this spare storage area from now on. Since the reliability of data retention can be maintained, data can be rewritten more times than the life of the EEPROM itself with high reliability.

Furthermore, according to the present invention, if a malfunction occurs in the EEPROM for data retention, it can be detected and the data can be corrected, which has the effect of improving the reliability of data retention.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an IC chip in an IC card according to a simple embodiment of the present invention, and FIG.
Figure 3 is an example of how an EPROM is divided into areas according to purpose of use. Figure 3 is an example of how a defective address map in the PROM shown in Figure 1 is expressed. Figure 4 is an example of data read and write processing in an EEPROM. The flowchart and FIG. 5 are diagrams showing the configuration of devices within an IC chip in an IC card according to another embodiment of the present invention. 11.61...CPU, 13.63...ROM, 1
4゜64...RAM, 15,65.66...EEP
ROM. 16...PROM.

Claims (2)

[Claims] 1. ROM that stores the CPU, input/output devices, and programs
In an IC card in which an IC chip consisting of a RAM for temporarily holding data and an EEPROM for storing data is attached to a plastic board, a PROM for storing a defective memory address in the EEPROM and its replacement address on the IC chip. An IC card characterized by being provided with. 2. ROM that stores the CPU, input/output devices, and programs
In an IC card in which an IC chip consisting of a RAM for temporarily holding data and a first EEPROM for storing data is attached to a plastic board, the first EEPROM is attached to a plastic board.
A second EEPROM and the first EEPROM that store the same information with the opposite logic to the information stored in the ROM.
An IC card characterized in that means for comparing the contents of the second EEPROM with the contents of the second EEPROM is provided on the IC chip.