JPH05210966A - Memory device - Google Patents

Abstract

PURPOSE: To speed up a memory system by preventing the increase of capacitance load to be driven by an address driver, etc., of an array even when the number of memory devices incorporated in the memory array are increased. CONSTITUTION: The memory devices 201 are connected in series in the memory array, and address, data, control command and clock, etc., are transmitted in a single direction among the series-connected devices. These data multiplexed and inputted by the device 201 are demultiplexed by a state machine 215, and when the relevant device is addressed, proper operation is performed. The state machine 215 multiplexes again the inputted address data, etc. When read- out is performed in the relevant device, the read out result is multiplexed also together. Further, a clock regenerative part 213 generates the clock to be used when the multiplexed result is sent to the device of a next stage.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to integrated circuit memory devices. In particular, the present invention relates to memory device architectures suitable for use in high speed cache memory systems and the like.

[0002]

BACKGROUND OF THE INVENTION In the design of high speed computer systems, much attention is paid to the realization of memory subsystems. Due to the recent acceleration of CPU, CPU
In order not to slow down the processing speed of, it is necessary to use a very fast memory device. However, designers often cannot afford to use the fastest device everywhere memory is needed in a computer system due to cost constraints. The two major factors that affect the price of a memory device are the capacity and speed of the memory device. Once capacity is determined, speed will be a major cost driver.

Designers therefore face a cost-performance trade-off. One way to achieve maximum performance while keeping costs at a reasonable level is to use a multi-level approach that uses very fast devices at one level and slower and less expensive devices at other levels. To realize the memory subsystem that was used.
The fastest devices are typically used in memory called the cache system, while the slower devices are used in the computer's main memory. The present invention relates to devices particularly suitable for use in cache memory systems.

Traditionally, designers of high speed memory arrays have faced many difficult problems, one of which is the line load problem. Each input of the memory device is associated with certain electrical characteristics such as capacitance, required drive current and voltage. To achieve the desired storage capacity, memory elements are added in parallel to the memory array, which also increases line capacitance and required drive current. The addition of memory devices necessarily increases the length of the driveline conductors for connecting the additional devices to the array. This conductor also adds capacitance and inductance to the input network in proportion to its length.

Address line driver devices are used to drive the common address lines of one or more rows of memory devices. To meet the timing requirements of the memory device, the address driver must be able to quickly charge and discharge the address line capacitance. In practice, this is extremely difficult, resulting in an effective access time of the memory device that is longer than the single device specification access time.

Voltage reflections due to the long conductors required to interconnect memory devices are also a problem. If the lines are not properly terminated, voltage reflections can occur on the address and data lines, damaging the memory device. Reflection can be prevented by properly terminating the address line and the data line, but modeling the line conductor is complicated, and the impedance of the line changes due to variations in the production process. It is difficult to know what to do.

These problems cause the problem that the memory system is not optimized in terms of access speed or convenience in design and manufacturing, and its capacity is limited.

[0008]

An object of the present invention is to provide a memory device that allows a memory system to utilize the access speed of individual memory devices. This memory device allows designers great flexibility to design a memory system that is easy to manufacture and that can be sized according to the desired storage capacity, rather than due to the constraints that come from the line driver device. ..

[0009]

SUMMARY According to one embodiment of the present invention, a memory device is provided that employs a unidirectional signal stream of multiplexed information. This information comes from the memory controller,
Delivered from one device to the next until all devices in the system are reached. When this information reaches all devices, it is returned to the memory controller. The memory controller sends both the address signal and the command signal to the first memory device via the common signal line. The memory device can receive command, address and data information via a command line or a dedicated data input line. If the command is directed to the memory device as determined by the chip select input on the device, the internal state machine performs the work required by the command, such as storing or reading data. .. read
In the case of a command, in response, data is returned from the memory and added to the multiplexed information,
Or sent to the next device by a separate information path.

The memory device regenerates the signal sequence (command-address-data) in synchronism with the received clock signal, and sends these signals along with the regenerated clock signal to the next memory device, which causes the information Ensures that the time relationship between the information and the clock is maintained when is sent to the next device. The operation of sending command, address and data information from device to device with clock signals in this manner continues until the end of the chain is reached at the memory controller or CPU.

By chaining the memory devices in this manner, each output driver needs to drive only one input, significantly reducing the capacitive loading on the signal lines compared to conventional parallel designs. You can Since each memory device is connected as a unidirectional chain, the length of the line conductors between the devices is very short, greatly reducing the voltage reflection problem. Also, this memory design allows for almost unlimited memory array sizes.

In large memory systems, ensuring data integrity is an important design goal. The memory device of the present invention provides a regenerated copy of the original multiplexed data to the CPU or memory controller, which can then use the data to check for errors. Each memory device can also be provided with a parity output that monitors to detect data errors.

Although the present invention is described as being implemented in a cache memory environment, it can be implemented in other environments. Hereinafter, the principle of the present invention will be described in detail with reference to the accompanying drawings by its embodiments.

[0014]

DETAILED DESCRIPTION OF THE INVENTION As shown in the accompanying drawings for illustrative purposes, the present invention is embodied in a novel memory device. This memory device of the present invention solves many of the problems encountered in implementing high speed memory arrays and is particularly well suited for use in computer cache memory systems.

FIG. 1 illustrates a prior art memory array in the form found in many computer systems. The line driver 101 includes a plurality of memory devices 103 to 117.
Drive the address line 102 connected to. Address line 102 represents another address line (not shown) used in this type of array. In general, each memory device has an address input connected to a common address driver. In a system using a 1 Mbit memory device, 20 address drivers may be provided, one for each address line required by the memory device.

The load problem associated with a typical memory system is also illustrated in FIG. In this figure, the line driver 101 drives the address inputs of eight memory devices 103-117. In practice, such line drivers are connected to more than the eight memory devices shown and have to drive many times the load imposed by the individual memory devices. Of particular concern is the amount of capacitance that the driver 101 must charge and discharge.
Given that one memory device has an input capacitance of 2-3 pf, the line driver must be able to charge and discharge a capacitance of 16-24 pf to drive eight memory devices as shown. If this operation is not performed within nanoseconds, the effective access time of the memory array will be longer than the specified access time of the individual devices that form the array. As already mentioned, the line driver must be connected to more than eight memory devices and usually be able to drive capacitive loads of 100 pf or more.

Of course, the line loading problem can be solved by using more line drivers. However, this is rarely a practical solution. The space available on a printed circuit board is limited and often there is not enough space on the board to add components. Adding components increases the cost of the product and reduces its reliability. Also, the problem of line loading is just as important for data lines. In this type of memory array, the output driver inside the memory device must drive a data line common to many other memory devices. Larger arrays inevitably introduce more capacitive load on the data lines, resulting in a delay in bringing valid data to the CPU.

FIG. 2 illustrates a memory device 20 according to the present invention.
1 shows an example. The memory device 201 has three sets of input lines, that is, a device address select input 203,
It has a clock input 205 and a multiplex input 207. In addition, the memory device 201 has two sets of output lines,
That is, clock output 209 and multiplex output 2
11 is provided.

Inside the memory device 201, a clock regeneration unit 213, a state machine 215, a random access memory array (RAM) 217 and an output data latch 219 are provided. Clock regeneration unit 213
Receives a clock input from the clock input line 205,
After delaying the clock signal, the clock output line 20
9 is sent. The RAM array 217 stores the data sent to the memory device. RAM array 217 can be made to any convenient size, such as 64K x 32 bits. The data being read from the RAM array 217 is held in the data latch 219. This latch 219
Is used as a convenient temporary holding area before outputting the data to the multiplex output line 211.

The state machine 215 is the memory device 2
01 controls the internal operation. Multiplex input line 20
All the information input from 7 is regenerated by the state machine 215, and is temporally associated with the regenerated clock and sent out on the multiplex output line 211. Data entered via multiplex input line 207 for storage in memory device 201 is stored by state machine 215 in a RAM array. When the read command is addressed to the memory device 201,
The state machine 215 loads the requested data into the data latch 219 and sends it to the multiplex output line 211.

The input / output of the memory device 201 is characteristically multiplexed with multiplexed command, address and data signals on the same serial input line 207. The memory controller or cache controller 221 sends an address including a bank address via the multiplex input line 207, and subsequently sends a command and further data as necessary. This data is loaded into the memory device 201 in synchronization with the clock by applying a clock signal on the clock input line 205.

In the exemplary embodiment of the present invention, the combined command and address information is 24 bits long, and each clock pulse is clocked into the memory device 201 by 3 clock pulses of approximately 2 nanoseconds. A pulse is needed. If the write data is sent to the memory device 201, then 2 nanosecond clock pulses are needed, one pulse for every 8 bits of data.

The state machine 215 compares the received address with a select code determined by the state (0 or 1) of the select code line 203. When the received address matches the select code, the state machine 21
5 performs the requested function. This function is typically an operation such as writing input data to the internal RAM array 217 or reading data previously stored in the internal RAM array 217.

If desired, the state machine 215 can increment the received address to allow reading or writing of blocks of almost any length of data. In order to fill the RAM array 217 with a known value, a load clear word (load-c
It is also possible to program additional functionality into the state machine, such as a rear word).

The memory device 217 outputs the received control sequence (address, address,
Command and data), and also the data requested by the read command to be read from the device 201. This information is multiplexed in the same order that it was entered. Therefore,
If the select code of the upstream memory device does not match the received address, then the device that is placed in series with it and that has the select code that matches this address responds. This feature allows the construction of memory arrays of almost any length.
By regenerating the clock, the time relationship between the information appearing on the multiplex output line 211 and the clock output line 209 will be approximately the same as the time relationship between the information input on the multiplex input line 207 and the clock input line 205. Become.

FIG. 3 shows an embodiment in which the present invention is applied to a bank row in order to achieve a wider data width. For example,
Assuming that the memory device 201 has a data width of 32 bits, two bank columns 303 and 305 of the memory device 201 can be used to achieve a width of a 64-bit word. The memory controller 321 sends the clock and multiplex information to each bank row, and if the read command has been sent to the bank row, then assembles the data returned from these bank rows to the desired word width. The address, command and data information is returned to the controller 321, thus verifying the integrity of the data. This structure is also suitable for incorporating other devices that follow the same protocol into the data stream as needed.

The synchronization of the devices in the chain is done by the state machine in each device. To that end, a special command, defined as no operation (NOP), is sent to these memory devices 201 until the state machines of all the devices in the chain reach the start state. When the first command arrives from the memory controller 321, the state machine in the memory device determines the length of operation and the timing at which the next command is expected to be delivered. The memory controller 321 can send the next command immediately or a series of NOP commands until the controller 321 is ready to start the next transaction. Addresses, commands, and data are sent from the controller 321 to memory devices on the same multiplex line, so all memory devices are synchronized so that each memory device can separate the data stream and check the addresses, commands, and data. It is necessary to let

FIG. 4 shows another embodiment of the present invention. In this embodiment, the memory controller 400 stores addresses, commands and write data in the memory device 40.
Send to 1. As mentioned previously, these addresses, commands and write data can be either three or four as required.
The memory device 401 is loaded in synchronization with the clock by one or more clock pulses.

When the address received by memory device 401 matches the code on chip select input 415, memory device 401 either stores the received data or outputs the requested data onto data output line 403. The memory device 421 is the memory device 401.
From the data input line 423, and sends the data to the next memory device 431 via the data output line 425. Each subsequent memory device sends data one after another in the same manner. Device 4
The address, command, and data supplied to 01, if the addresses match, from the memory device 401 to other subsequent memory devices 421 and 431 in the chain.
Is delivered to.

If the received addresses do not match, the memory device 401 sends the address, command and data input to the input line 405 through the output line 407.
Each memory device passes the multiplexed information to the next device by the same operation.

If desired, each memory device may be provided with a parity output line 413. The memory device signals on this parity output line when a memory error is detected by the device. The memory controller 400 can determine whether a memory error has occurred by monitoring the parity output line.

FIG. 5 shows another embodiment of the present invention. The memory device 501 is provided with 5 sets of input lines and 6 sets of output lines. The multiplex input 503 is composed of eight input lines for command, address and write data, plus one parity line, for a total of nine lines.
Clock input line 505 receives a clock signal at approximately 500 MHz which is synchronized with the information on multiplex input 503. Further, read data 507 including eight data for receiving data and the ninth data for parity is also provided. Address select input line 509 is hardwired to program memory device 501 to respond to a particular memory address. The fifth input line is the reset line 511.

Also, the six sets of output lines are as follows: 1) Read data output line 513 with one width for parity added to eight widths for data. This output line carries the data resulting from a read or other command. 2) Multiplex output line 5 with one line for parity added to eight lines for command, address and write data information
15. This output carries a copy of the information received on the multiplex input line 503. 3) Clock output 517. This output carries a clock signal synchronized with the information on the multiplex output line 515 and the read data output line 513. 4) Parity output 519. When the memory device 501 detects a parity error, a signal is sent to this output. 5) Frame output 521. The signal on this output indicates the beginning of the data stream. 6) Status output 523. A signal coded according to the definition of the data being sent by the memory device 501 is sent to this output.

All signal lines to and from memory device 501 are unidirectional. Typically, the multiplexed input information is a command followed by an address,
When the command is write, it is further composed of data. The output is some data obtained by executing the read command, information related to this transaction, and the like. An internal state machine (not shown) controls the internal operation of the memory device 501 and is programmed to perform useful functions such as reading data from consecutive memory locations by giving only one command and address. To be done.

The memory device 501 executes the following commands. Read N (reads an N-bit word at the received address and shifts it out with four clock pulses per byte, N is a multiple of 32, up to 2
It can take up to 56 bits. ) ● Read 32 Replace (reads the word starting at the received address and replaces it with incoming data) ● Compare and Swap (reads a 32-bit word starting at the received address and compares the word with the prepared comparison data) If the words match, replace with the prepared exchange data. In any case, the read result is returned.) ● Pass 32 (pass the data on the input line to the output side. This data is stored. ● Write 32 Mask (write the selected byte corresponding to each bit set in the mask up to 4 bytes starting from the received address) ● Write XX (XX starting at the received address)
Write a bitword. ● Write XX Pass (new data is overwritten on the data of the received address, and the new data is passed to the output side.) ● Idle (NOP) (do nothing)

A typical stream of multiplexed information sent to the memory device 501 by a memory controller (not shown) for "Write 32" is detailed in the following table. In the table, each column represents one clock pulse.

[0037]

Cx is a bit representing a command. Ax is a bit that represents an address. P is the parity bit of the byte sent. Lx is the length of the transaction, which is 1, 2, 3 or 4 cycles. Mx is a write mask, each bit of which indicates the byte to be written. X is a reserved bit that is not used. Sx is a memory device select code, and the memory device 501
This code must match the address select input line 509 for the command to respond to the command. D is a data bit sent to the memory device 501.

The reset input 511 is the memory device 50.
It is used to initialize a 1 to a known state and make the command ready for execution. Since the memory device 501 is perfectly synchronized, its operation is controlled by the command data and sequence input to the input ports 503 and 507. The memory device 501 is programmed according to the length of time each transaction takes to
The memory controller is N during periods when access is not required.
Send an OP command.

In FIG. 6, a plurality of memory devices as shown in FIG. 5 are connected in series. The memory controller 531 sends the multiplex information and the clock to the memory device 501A. Memory device 501
A uses the multiplexed information and clock for the next device 5
01B, and device 501B sends it further to device 501C. Output of memory device 501C (5
15C, 513C, 517C, 523C, 521C)
Are connected to the memory controller 531. Therefore, the memory controller 531 copies the first multiplex information and the memory devices 501A to 501C.
Receives all data read from. By monitoring the status output 523C from the memory device 501C and the frame output line 521C, the memory controller 531 can determine what information is input from the memory device 501C by reading data output 51.
Can be judged on 3C.

Although the present invention has been described with reference to the specific embodiments thereof, the present invention is not limited to these specific forms or arrangements of constituent parts illustrated and described in the present application. Various modifications and changes can be made without departing from the scope of the invention described in. For example, instead of using the external address select line to set the address of each memory device, a special address initialization sequence may be sent from the memory controller or other device with the same result. Therefore, the present invention can be implemented in a mode different from that described in detail in the present application.

[0042]

As described above in detail, according to the present invention, even if the scale of the memory array is increased, the load that the driver has to drive is kept to a small amount. A great effect can be obtained for speeding up.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a typical memory array according to the prior art.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram showing a memory array formed by interconnecting memory devices according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration in which a plurality of memory devices of one embodiment of the present invention are connected.

FIG. 5 is a diagram showing a pin arrangement of a memory device according to an embodiment of the present invention.

FIG. 6 is a diagram showing a memory array including a plurality of memory devices shown in FIG.

[Explanation of symbols]

101: Line driver 102: Address lines 103 to 117: Memory device 201: Memory device 203: Device address select input 205: Clock input 207: Multiplex input 209: Clock output 211: Multiplex output 213: Clock regeneration unit 215: State machine 217: RAM array 219: Output data latch 221: Memory controller or cache controller 305, 306: Bank row 321: Memory controller 400: Memory controller 401, 421, 431: Memory device 413: Parity output line 501: Memory device 503 : Multiplex input 505: Clock input line 507: Read data 509: Address select input line 511: Reset line 513: Read Data output line 515: Multiplex output line 517: Clock output 519: Parity output 521: Frame output 523: Status output 531: Memory controller 501A, 501B, 501C: Memory device

Claims (8)

[Claims] 1. A memory device comprising the following (a) to (e): (a) clock input means for receiving a clock signal; (b) serial input means for inputting serial information; (c) data storage. Means; (d) serial output means; (e) state machine means for performing the following operations (a) to (d): (a) serial received using the received clock signal through the serial input means (A) store the received data in the data storage means according to the received data store command; (c) read the data from the data storage means according to the received data read command; D) The serial information is regenerated, and the output signal carrying the regenerated serial information is transmitted from the serial output means. 2. A clock output means and a clock regeneration means are provided, the received clock signal is regenerated, and the regenerated clock signal is sent out through the clock output means. Item 2. The memory device according to Item 1. 3. The memory device according to claim 1, further comprising a parity output unit used for detecting a data error. 4. A memory device according to claim 1, further comprising chip select means for externally programming a response to the memory address. 5. A memory device provided with the following (a) to (f): (a) clock input means for receiving a clock signal; (b) serial input means for inputting serial information; (c) data storage. Means; (d) serial output means; (e) data output means; (f) state machine means for performing the following operations (a) to (d): (a) using the received clock signal, the serial Demultiplex serial information received through the input means; (a) store the received data in the data storage means according to the received data store command; (c) store the data according to the received data read command. The data is read from the data storage means, and the data is sent from the data output means; (d) The serial information is regenerated and the regenerated serial information is output. A force signal is transmitted from the serial output means. 6. A clock output means and a clock regeneration means are provided, the received clock signal is regenerated, and the regenerated clock signal is sent out through the clock output means. Item 5. The memory device according to item 5. 7. The memory device according to claim 5, further comprising a parity output unit used for detecting a data error. 8. The memory device according to claim 5, further comprising chip select means for externally programming a response to the memory address.