JPH0414924A - Synchronization protective circuit - Google Patents

Abstract

PURPOSE:To revise a synchronous pattern and a protective stage number optionally by reading a specific bit pattern stored in a random access memory sequentially, comparing the pattern with an extracted synchronous bit pattern and detecting the synchronization so as to revise the storage content of the random access memory properly. CONSTITUTION:This circuit is provided with a synchronous bit extracting means 111, a random access memory 121, a comparing means 131, a setting means 141 and a synchronization detecting means 151. Then a specific bit pattern stored in the random access memory 121 is sequentially read and compared with the extracted synchronous bit pattern to apply synchronization detection, thereby properly revising the storage content of the random access memory 121. Thus, the synchronous pattern and the protective stage number are implemented optionally.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples Effects of the Invention [Summary] Has various synchronization patterns Regarding a synchronization protection circuit that can be used with one or more devices, the purpose is to arbitrarily set the synchronization pattern and the number of protection stages. A random access memory that stores a part of the pattern and its own address where the next part of this predetermined pattern is stored, a predetermined pattern included in the data read from the random access memory, and a synchronized bit extractor. and a comparison means that detects a match between the synchronization bits extracted by the means, and a comparison means that selects its own address included in the data read from the random access memory when a match is detected by the comparison means; Address setting means selects a predetermined address and inputs it into the random access memory when a mismatch is detected; and detects synchronization establishment when the data read from the random access memory reaches a predetermined value; and a synchronization detection means for occasionally detecting out-of-synchronization.

[Industrial Application Field] The present invention relates to a synchronization protection circuit that can be used with one or more devices having various synchronization patterns.

In the reception synchronization control section of a digital communication device, a technique is commonly used in which a specific pattern is inserted into one frame on the transmitting side in order to achieve frame synchronization, and this pattern is detected on the receiving side to identify the frame. There is. The synchronization protection circuit is used in such a reception synchronization control section to avoid erroneous synchronization and maintain a normal synchronization state.

In recent years, with the development of the information industry, the number of devices connected to many networks has increased, and synchronization protection circuits must also support each synchronization pattern, so it is necessary to share circuits and provide versatility. be.

[Prior Art] A general synchronization protection circuit includes a pattern comparison circuit that compares a 1-bit or multiple-bit synchronization pattern extracted from data with a specific pattern, and a pattern comparison circuit that retains the comparison result for the number of protective films to prevent synchronization or loss of synchronization. The device is equipped with forward and backward protection circuits that detect the establishment of synchronization. Here, the pattern comparison circuit is realized by a combination of a decoder or a shift register and a logic gate, and the forward and backward protection circuits are realized by a combination of a counter or a shift register and a logic gate.

For example, when the pattern comparison circuit is implemented using a decoder, a predetermined number of input synchronization bits/7 bits are held, and the held multiple bits/7 bits of data are input to the decoder. Therefore, pattern comparison can be performed by using a decoder that outputs a matching signal when input data is a specific pattern. In addition, when the forward and backward protection circuits are implemented using counters, the counters count the continuously output match signals or mismatch signals, and when a predetermined count value is reached, synchronization is established or synchronization is detected. I do.

(Problems to be Solved by the Invention) By the way, in the conventional method described above, since the synchronization protection circuit is configured by hardware, there is a problem that the specific pattern to be compared and the number of protection stages are fixed. Therefore, when trying to perform synchronization detection for several types of synchronization patterns or the number of protection stages, the above-mentioned synchronization protection circuits must be prepared according to the types of synchronization patterns or the number of protection stages, which requires expansion of the circuit scale. I will invite you.

As a prior art technique in which the number of protection stages is made variable to reduce the circuit scale, there is a synchronization protection circuit disclosed in Japanese Patent Laid-Open No. 61-276435. This synchronization protection circuit allows you to freely set the number of protection stages by determining the timing to reset the counter using the counter reset circuit, but it is only by making both the synchronization pattern and the number of protection stages variable that synchronization for any communication destination can be achieved. Detection is realized, and a synchronization protection circuit that can set both of these functions arbitrarily has been desired.

In addition, as a conventional technique that allows the synchronization pattern and the number of protection stages to be easily changed,
There is a frame synchronization circuit disclosed in the above publication. This frame synchronization circuit uses programmable read-only memory to set the synchronization pattern and the number of protection stages, so it has the advantage of being able to easily respond to design changes, etc. However, it is connected to multiple communication destinations and can be adjusted as needed. It is not possible to handle cases where the combination of synchronization pattern and number of protection stages is changed each time. Therefore, a synchronization protection circuit that can appropriately switch between a plurality of synchronization patterns and the settings of the number of protection stages has been desired.

The present invention was created in view of these points, and an object of the present invention is to provide a synchronization detection circuit in which the synchronization pattern and the number of protection stages can be arbitrarily set.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the synchronization protection circuit of the present invention.

In the figure, synchronization bit extraction means 111 extracts synchronization bits from input data.

The random access memory 121 stores at each address a part of a predetermined pattern and its own address where the next part of the predetermined pattern is stored.

The comparison means 131 receives a predetermined pattern included in the data read from the random access memory 121 and the synchronization bit extracted by the synchronization bit/node extraction means 111, and detects a match between them.

The address setting means 141 sets the random access memory 121 when a match is detected by the comparing means 131.
When a mismatch is detected, a predetermined address is selected and input to the random access memory 121.

The synchronization detection means 151 is a random access memory 121
Establishment of synchronization is detected when the data read from reaches a predetermined value, and loss of synchronization is detected at other times.

Therefore, the overall configuration is such that synchronization detection is performed by sequentially reading specific patterns stored in the random access memory 121 and comparing them with extracted synchronization bits.

[Operation] Each storage area of the random access memory 121 stores a part of a predetermined pattern necessary for synchronization detection and its own address to be accessed next. Therefore, by inputting the address read together with the predetermined pattern to the random access memory 121 itself via the address setting means 141, the continuous predetermined pattern can be sequentially read out. The comparison means 131 compares the read predetermined pattern with the synchronization bit extracted by the synchronization bit extraction means 111, and as long as the matching state continues, reading of data from the above-mentioned random access memory 121 continues. When this read data reaches a predetermined value, the synchronization detection means 151 detects the establishment of synchronization.

Further, when a mismatch state is detected by the comparison means 13■ during the synchronization detection operation described above, the address setting means 141
Since a predetermined address is selected by , the synchronization detection operation is repeated by returning to this address.

In the present invention, synchronization is detected by sequentially reading out specific patterns stored in the random access memory 121 and comparing them with the extracted synchronization bits. By appropriately changing the synchronization pattern and the number of protection stages, it is possible to arbitrarily change the synchronization pattern and the number of protection stages.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a synchronization protection circuit in one embodiment of the present invention.

In the figure, 211 is a synchronization bit extraction circuit, 221 and 251 are random access memories (RAM), and 23
1 and 235 are selectors, 233 is an exclusive OR gate, 241 and 245 are buffers, 243 is a flip-flop (FF), 261 is a coincidence detection circuit, 27
1 indicates a pulse generating circuit (PC;), respectively.

The synchronous bit extraction means 111 shown in FIG.
In AM221, the comparison means 131 is an exclusive OR gate 2.
33, the address setting means 141 selectors 231, 2
35, the synchronization detection means 151 corresponds to the coincidence detection circuit 261, respectively.

The synchronization bit extraction circuit 211 is for extracting synchronization bits from input data.

The RAM 221 is for storing a specific pattern for synchronization detection, and each bit of the specific pattern is stored together with the storage address of the next bit. In other words, when certain data is read, one bit of it is used as one bit of a specific pattern, and the data other than this l bit is used as the address from which to read the next one bit of the specific pattern. ing.

The selector 231 selects the address terminal AO- of the RAM 221.
This is for selecting the address to enter in A7.
When rewriting the contents of RAM221, the central processing unit (
CPtJ (not shown), and otherwise selects the output of the selector 235.

The exclusive OR gate 233 compares the synchronization bit extracted by the synchronization bit extracting circuit 211 described above with one bit of a specific pattern read from the RAM 221, and obtains an exclusive OR output of the two. . That is, when the extracted synchronization bit 7 and the read specific pattern are equal, a logic "0" is output.

The selector 235 performs a selection operation according to the output logic of the exclusive OR gate 233. Exclusive OR gate 233
If the output logic is “°0” (when the synchronization bit and the specific pattern are equal), select the output of RAM251,
When the output logic is "'1", predetermined fixed data is selected.

The buffer 241 is used to input data output from the CPU to the data terminals DO to D7 of the RA and M221 when rewriting the contents of the RAM 221, and otherwise puts its own output terminal in a high impedance state. Disconnect from the CPU side.

The flip-flop 243 is for taking in and holding data output from the RAM 221, and the held contents are inputted to the data terminal Do-D7 of the RAM 251 via the buffer 245.

The coincidence detection circuit 261 is for detecting synchronization establishment and synchronization loss based on the output of the RAM 221 held in the flip-flop 243, and detects the above-mentioned synchronization depending on whether the output content of the RAM 221 is equal to a predetermined pattern. Perform detection.

The pulse generation circuit 271 generates various control signals for giving operation instructions to each of the above-mentioned components. Specifically, the frame clock FCLK is sent to the synchronization bit extraction circuit 211, and the select signal *SEL (signal of negative logic *
) to the selector 231 and buffer 241, write enable signal *FRWE to RAM
To 221, Lanochikronk*LCK is 7 buflo,
A write enable signal *MFWE is input to the buffer 245 and RAM 251 through the buffer 243 .

Next, the operation of the embodiment of the present invention described above will be explained.

FIG. 3 shows the operation timing of one embodiment.

The operation of the embodiment will be described below with reference to FIGS. 2 and 3.

The synchronization bit extraction circuit 211 receives each input frame a.
, b, . . . is extracted from the data at the timing when the frame clock FCLK rises (FIGS. 3(a), (b), and (C)).

Also, the frame number corresponding to each frame data is RA
An address is input to M251 (FIG. 3(d)), and 8-bit data containing a specific pattern for comparison with the extracted synchronization bits is read out. Here, the most significant bit of the 8-bit data corresponds to a specific pattern, and the other 7 bits correspond to the address of the RAM 221 where the next specific pattern of the frame of interest is stored.

Only the most significant bit of the data read from the RAM 251 is input to the input terminal of the exclusive OR gate 233, and if this most significant bit matches the extracted synchronization bit, the other bits are input to the input terminal of the exclusive OR gate 233. 7 bits is input to the RAM 221 as an address via selectors 235 and 231.

Next, the RAM 221 outputs the data specified by the address input via the selector 231, that is, the next synchronization pattern of the frame of interest and the address of the RAM 221 itself in which the next synchronization pattern is stored.

The flip-flop 243 captures and holds this output data in synchronization with the falling edge of the latch clock*LCK output from the pulse generating circuit 271, as shown in FIG. 3(e).
), furthermore, the RAM 251 is connected to this flip-flop 243
The held data is stored in synchronization with the falling edge of the write enable signal *MFWE, and the data corresponding to the frame of interest is updated (FIGS. 3(f) and (g)).

In the example shown in FIG.
M (N corresponds to multiple bits on the upper side, M corresponds to multiple bits on the lower side) is read out, and the specific synchronization pattern stored in this address NM and the address N (M±1 ) is read out and further stored in RAM25.
It is stored in 1. In this way, by sequentially updating the lower address M up to M10 when focusing on a certain frame, a synchronization protection circuit with as many protection stages as the number of protection stages is realized.
The match detection circuit 261 detects that the lower address has become equal to or greater than M, and synchronization is established.

In addition, when an out-of-synchronization occurs and a mismatch occurs between the extracted synchronization bit and a predetermined pattern, the selector 235
Since the fixed data is selected by , the above-described synchronization detection operation for each protection stage is repeated from the beginning.

By the way, the read data from the RAM 221 described above needs to be finalized when the data is taken into the flip-flop 243. Therefore, at timings other than when the data is removed, new data can be written to the RAM 221 to change the stored contents. Pulse generation circuit 271
The write enable signal *FRWE and the select signal *SEL outputted from the controller are signals for controlling this write operation (FIGS. 3(h) and (i)). When the logic of the select signal *SEL becomes 0", data and address from the CPU are input to the RAM 221 via the Hanwha 241 and the selector 231, and then data is written to the RAM 221 at the timing when the write enable signal *FRWE falls. will be held.

FIG. 4 shows the flow of operations up to the establishment of synchronization when focusing on the address read from the R, AM 221. The two-digit number shown in the figure represents 7-bit data excluding the most significant bit of the 8-bit data stored in the RAM 221. The lower digits shown correspond to the lower 4 bits.

If the synchronization bit and the specific pattern do not match, the output logic of the exclusive OR gate 233 is "1", so
Fixed data ``00j'' (all 7 bits are ``0'') is selected by the selector 235, and this fixed data is input to the RAM 221 as an address. RAM22
The area of address ``00'' of 1 stores the address ``01'' where the first 1 bit of the specific pattern and the next 1 bit of the specific pattern are stored, and the synchronization bit to be extracted is the first bit of the specific pattern. this data until it matches
Data reading is repeated.

Once the synchronization bit equal to the first bit of the specific pattern is extracted, the addresses are sequentially updated based on the data stored in the RAM 221. The horizontal part shown in FIG. 4 indicates one protection stage corresponding to one multiframe, and synchronization is established only when the last row is reached. Thereafter, this last column is visited until the synchronization is lost, and when the synchronization occurs, the synchronization detection process is repeated by returning to the first address "00".

In this way, the RAM 221 stores a specific pattern in a part of the data read from the RAM 221, and stores the specific pattern to be read next in the remaining part.
Store your own address. Therefore, synchronization can be established by sequentially reading specific patterns based on this storage address. In addition, by controlling the buffer 241 and the selector 231 with the pulse generation circuit 271,
The contents stored in the RAM 221 can be changed in parallel with the synchronization establishment operation. Therefore, by changing this stored content, it becomes possible to arbitrarily set a specific pattern for synchronization detection and the number of synchronization protection stages.

In addition, in the embodiment of the present invention described above, in order to perform synchronization detection for input data having a multi-frame configuration,
Although data related to each frame read from the RAM 221 is temporarily stored in the RAM 251, the present invention can also be applied to cases where synchronization detection is performed on frame data that is input continuously. can.

In this case, the RAM 25] may be omitted and the output of the buffer 245 may be directly returned to the RAM 221 side.

In addition, in the embodiment, the RAM 22 is
I tried to rewrite the contents of 1, but the synchronization detection operation and R
AM22 ] update operation may be performed separately, and even in this case, the advantage of being able to arbitrarily set the synchronization pattern and the number of protection stages remains unchanged.

[Effects of the Invention] As described above, according to the present invention, specific patterns stored in a random access memory are sequentially read out,
Synchronization is detected by comparing it with the extracted synchronization bits, and the synchronization pattern and the number of protection stages can be changed arbitrarily by appropriately changing the contents stored in the random access memory. Extremely useful.

[Brief explanation of the drawing]

Figure 1 is a principle block diagram of the synchronization protection circuit of the present invention, Figure 2 is a block diagram of the principle of the synchronous protection circuit of the present invention.
FIG. 3 is a block diagram of a synchronization protection circuit according to an embodiment of the present invention, FIG. 3 is an operation timing chart of the embodiment, and FIG. 4 is a diagram showing the flow of operation of the embodiment. 141 is an address setting means, 151 is a synchronization detection means, 211 is a synchronization bit extraction circuit, 221 251 is a RAM, 231 235 is a selector, 233 is an exclusive OR gate, 24], 245 is a buffer, 243 is a flip-flop ( FF), 261 is a coincidence detection circuit, and 271 is a pulse generation circuit (PC). In the figure, 111 is a synchronization bit extraction means, 121 is a random access memory, 131 is a comparison means,

Claims (1)

[Claims] (1) A synchronization bit extracting means (111) for extracting synchronization bits in input data, and each address stores a part of a predetermined pattern and its own address in which the next part of this predetermined pattern is stored. The predetermined pattern included in the data read from the random access memory (121) and the synchronization bit extracted by the synchronization bit extracting means (111) are inputted to a random access memory (121), and these Comparison means (131) for detecting a match between
and when a match is detected by the comparing means (131), selects its own address included in the data read from the random access memory (121), and when a mismatch is detected, selects a predetermined address. an address setting means (141) for selecting and inputting the address into the random access memory (121); and detecting establishment of synchronization when data read from the random access memory (121) reaches a predetermined value; Synchronization detection means (151
), and a synchronization protection circuit comprising: