JP2004152420A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, in which an optional refresh address can be set to a refresh counter and it can be output to the outside, in a semiconductor device comprising a memory cell part which needs refreshing. <P>SOLUTION: The semiconductor device comprises the refresh counter 11 for holding a refresh address for selecting one group of a memory cell part divided into a plurality of groups; an address buffer 12 for fetching an external address from an address input terminal 16 and holding it; and a control circuit 15 which has a function of taking an external signal from a plurality of command input terminals 18 and 19 and setting the external address of the address buffer 12 to the refresh counter 11, when the state of the external signal matches with the prescribed combination. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a memory cell portion requiring refresh, and more particularly to a semiconductor device having a function of performing auto refresh, self refresh, and the like using a refresh counter.
[0002]
[Prior art]
2. Description of the Related Art A semiconductor device having a DRAM cell (dynamic memory cell) requires a refresh operation for rewriting cell data at regular time intervals. There are three types of refreshing: a ras-only refresh in which an address to be refreshed is input from the outside each time, an auto-refresh in which only a refresh timing is input, and a self-refresh used in a standby state and automatically refreshed only inside. The method is well known. In recent synchronous types, auto refresh and self refresh provided with a refresh counter therein are mainstream.
[0003]
FIG. 4 is a block diagram showing a configuration of an address control circuit of a conventional semiconductor device, and an input waveform diagram showing an auto-refresh entry method. In the conventional semiconductor device, as shown in FIG. 4A, a refresh counter 101 for holding a refresh address, an address buffer 102 for taking in and holding an external address, a refresh address or an external address are selected and output to an internal address bus 103. The switching circuit 104 has a control circuit 105 for controlling these according to a plurality of external signals.
[0004]
The refresh counter 101 holds an address of a memory cell portion to be refreshed next in the auto refresh and the self refresh, and outputs this to the switching circuit 104 as a refresh address. Further, upon receiving the signal from the control circuit 105, the refresh address held is counted up after the refresh operation is completed.
[0005]
The address buffer 102 has a plurality of address input terminals 106, receives a signal from the control circuit 105, takes in an input signal (hereinafter, referred to as "Add") of the address input terminal 106, and holds this as an external address. At the same time, the external address is output to the switching circuit 104.
[0006]
The switching circuit 104 receives a signal from the control circuit 105, selects one of a refresh address and an external address, and outputs the selected address to the internal address bus 103.
[0007]
The control circuit 105 has a clock input terminal 107 and a plurality of command input terminals 108. A clock signal (hereinafter referred to as CLK) input from a clock input terminal 107 is used for synchronizing the entire semiconductor device. The signals input from the command input terminal 108 define the operation of the semiconductor device according to the combination.
[0008]
For example, in a recent synchronous DRAM, as shown in the figure, three of / RAS, / CAS, and / WE are used, and main operations such as read, write, precharge, bank selection, auto refresh, and self refresh are performed. Is stipulated.
[0009]
The control circuit 105 generates and supplies necessary control signals to each circuit block of the semiconductor device including the refresh counter 101, the address buffer 102, and the switching circuit 104 in FIG. 4A according to these input signals. .
[0010]
Here, only the necessary circuit blocks and input signals around the refresh counter are shown.
[0011]
FIG. 4 (b) is an input waveform diagram defining auto-refresh in the synchronous DRAM. At the rising edge of the clock signal (CLK) input to the clock input terminal 107, the signals / RAS, / CAS, and / WE are captured. When these are "0", "0", and "1", respectively, the auto refresh operation is started. At this time, the Add is not fetched and the external address of the address buffer 102 is not used internally.
[0012]
When the auto-refresh operation is started, first, the switching circuit 104 selects a refresh address output from the refresh counter 101 and outputs this to the internal address bus 103. Next, although not shown, a read operation is internally performed according to the timing of a control signal generated by the control circuit 105, and the memory cell portion corresponding to the refresh address is refreshed.
[0013]
In a DRAM, since a read operation also serves to rewrite a memory cell, it is not necessary to perform a write operation.
[0014]
Following the read operation, a precharge operation is automatically performed internally, and finally, the refresh address held in the refresh counter 101 is counted up, and the auto refresh operation is completed.
[0015]
In the case of the self-refresh, the timer circuit is provided inside the control circuit 105, and the operation of performing the refresh using the refresh address of the refresh counter 101 is the same except that the refresh timing is also generated by the timer circuit. is there.
[0016]
Such auto refresh and self refresh are convenient for the user because there is no need to input an external address, but have the serious disadvantage that the refresh address cannot be grasped in the evaluation and failure analysis at the product development stage. .
[0017]
In other words, if a defect occurs in a peripheral circuit, particularly the refresh counter 101, the internal address bus 103, or a part of the control circuit 105 related to the auto-refresh due to a variation in a manufacturing process or a minute defect, an enormous evaluation time is required. There has been a problem that a failure symptom cannot be confirmed except for the necessary memory map acquisition by reading and writing of all the cells.
[0018]
In addition, even when a failure analysis is performed due to a stylus hit of an internal signal, the refresh address cannot be grasped, so that the internal state cannot be controlled and efficient analysis cannot be performed. The read operation by inputting an external address is slightly different from the internal read operation in auto-refresh in the timing of the internal control signal and the like, and the failure symptom is not often reproduced, and often cannot be used as the failure analysis means. Was.
[0019]
In addition, in self-refresh, the refresh cycle by the timer circuit is usually set to be close to the limit of the ability of the memory cell in order to suppress the standby current. In some cases, this was a problem.
[0020]
[Problems to be solved by the invention]
As described above, the conventional semiconductor device has a problem that the refresh address cannot be grasped, and it takes an enormous amount of time to evaluate the auto-refresh and the self-refresh and analyze the failure.
[0021]
The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device that can set an arbitrary refresh address and output the refresh address to the outside.
[0022]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a refresh counter for holding a refresh address for selecting one of a plurality of groups of memory cell units, and a refresh counter for inputting an address from an address input terminal. An address buffer for holding an external address, a command input signal and a subcommand input signal are received, and based on the command input signal and the subcommand input signal, the external address held in the address buffer is used as a refresh address for the refresh counter. And a control circuit for controlling the setting.
[0023]
According to the present invention, an arbitrary address can be set in the refresh counter, so that evaluation and failure analysis can be performed efficiently, and a highly reliable semiconductor device can be realized.
[0024]
Further, the semiconductor device of the present invention includes a refresh counter for holding a refresh address for selecting one of the memory cell units divided into a plurality of groups, an output buffer for holding output data, a command input signal, A control circuit for receiving a sub-command input signal and controlling the refresh address held in the refresh counter to be output to the outside via the output buffer based on the command signal and the sub-command signal. And
[0025]
According to the present invention, since the refresh address held by the refresh counter can be read arbitrarily, the evaluation and the failure analysis can be performed efficiently, and a highly reliable semiconductor device can be realized.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0027]
(1st Embodiment)
FIG. 1 is a block diagram showing a configuration of an address control circuit of a semiconductor device according to a first embodiment of the present invention, and an input waveform diagram thereof.
[0028]
First, a circuit block diagram around the refresh counter will be described. As shown in FIG. 1A, the semiconductor device according to the first embodiment includes a refresh counter 11 for holding a refresh address, an address buffer 12 for taking in and holding an external address, and selecting a refresh address or an external address to select an internal address bus. And a control circuit 15 for controlling these according to a plurality of external signals.
[0029]
The refresh counter 11 holds an address of a memory cell portion to be refreshed next in the auto refresh and the self refresh, and outputs this to the switching circuit 14 as a refresh address. Further, in response to a setting signal from the control circuit 15, an external address is received from the address buffer 12, and the external address is reset as a refresh address. Further, after the refresh operation is completed, the held refresh address is counted up in response to the update signal from the control circuit 15.
[0030]
The address buffer 12 has a plurality of address input terminals 16, receives an input signal from the control circuit 15, receives an input signal of the address input terminal 16 (hereinafter referred to as "Add"), and holds this as an external address. At the same time, the external address is output to the switching circuit 14.
[0031]
In the present invention, the address buffer 12 is configured to receive the setting signal from the control circuit 15 and output the held external address to the refresh counter 11 via the signal line 12A.
[0032]
The switching circuit 14 receives a switching signal from the control circuit 15, selects one of the refresh address and the external address, and outputs this to the internal address bus 13 as an internal address.
[0033]
The control circuit 15 has a clock input terminal 17, a plurality of command input terminals 18, and a plurality of subcommand input terminals 19. A clock signal (hereinafter, referred to as CLK) input from the clock input terminal 17 is used for synchronizing the entire semiconductor device. The signals input from the command input terminal 18 and the subcommand input terminal 19 define the operation of the semiconductor device according to the combination.
[0034]
For example, here, as shown in the figure, / RAS, / CAS and / WE are command input signals to command input terminal 18, and BS0 and BS1 are subcommand input signals to subcommand input terminal 19. use. The command input signal defines main operations such as read, write, precharge, bank selection, auto-refresh, and self-refresh, and the sub-command input signal defines options for distinguishing details of the operation.
[0035]
The control circuit 15 generates and supplies necessary control signals to each circuit block of the semiconductor device including the refresh counter 11, the address buffer 12, and the switching circuit 14 according to these input signals.
[0036]
Here, only the circuit blocks and input signals required around the refresh counter 11 are shown.
[0037]
FIG. 1B is an input waveform diagram that defines auto-refresh in the first embodiment according to the present invention. At the rising edge of CLK, / RAS, / CAS, / WE, BS0, and BS1 are fetched, and if these are "0", "0", "1", "0", and "0", respectively, as in the conventional case. Auto-refresh operation is started. At this time, Add from the address input terminal 16 is not taken in, and the external address of the address buffer 12 is not used internally.
[0038]
When the auto refresh operation is started, first, the switching circuit 14 selects a refresh address output from the refresh counter 11 and outputs this to the internal address bus 13. Next, although not shown, a read operation is internally performed in accordance with the timing of a control signal generated by the control circuit 15, and the memory cell section corresponding to the refresh address is refreshed.
[0039]
When the memory cell section is a DRAM, it is not necessary to perform a write operation because the read operation also serves to rewrite the memory cell.
[0040]
Following the read operation, a precharge operation is automatically performed internally, and finally, the refresh address held in the refresh counter 11 is counted up, and the auto refresh operation is completed.
[0041]
Conventionally, the start command of the auto refresh operation did not require the input of BS0 and BS1, but in the present invention, in order to distinguish it from the addressing auto refresh described below, "0" and "0" are input to BS0 and BS1 as subcommand input signals. Specify "0".
[0042]
FIG. 1 (c) is an input waveform diagram defining an addressing auto-refresh in the first embodiment according to the present invention. In the semiconductor device according to the first embodiment, a subcommand for setting a refresh counter is additionally defined in an auto-refresh command, and control around the refresh counter is changed accordingly.
[0043]
First, at the rising edge of CLK, / RAS, / CAS, / WE, BS0, and BS1 are fetched. If these are "0", "0", "1", "1", and "0", respectively, The designated auto refresh operation is started.
[0044]
At this time, Add from the address input terminal 16 is taken in simultaneously, and is held in the address buffer 12 as an external address.
[0045]
The control circuit 15 first outputs a setting signal to the address buffer 12 and the refresh counter 11, and outputs the setting signal to the refresh counter 11 via the signal line 12A in order to set an external address of the address buffer 12 as a refresh address. Next, a switching signal is output to the switching circuit 14 to output the refresh address of the refresh counter 11 to the internal address bus 13.
[0046]
Thereafter, similarly to the above-described auto refresh operation, a read operation and a precharge operation are performed internally, and finally, the refresh counter 11 is counted up to complete the addressing auto refresh.
[0047]
Commands and sub-commands can be similarly defined for self-refresh. For example, in a synchronous DRAM that has become mainstream recently, the only difference between the entry commands of the auto refresh and the self refresh is the CKE (not shown). Therefore, the above-described definitions of the commands and subcommands can be used as they are.
[0048]
According to the first embodiment, an arbitrary address can be set as a refresh address, so that auto-refresh or self-refresh can be started from a specific address, and can be executed in a specific address range. Efficiency can be improved.
[0049]
(Second embodiment)
FIG. 2 is a block diagram showing a configuration of an address control circuit of a semiconductor device according to a second embodiment of the present invention, and an input waveform diagram thereof.
[0050]
First, a circuit block diagram around the refresh counter will be described. As shown in FIG. 2A, the semiconductor device according to the second embodiment includes a refresh counter 21 for holding a refresh address, an output buffer 22 for outputting data to the outside, and a refresh address from the refresh counter 21 for a plurality of groups. And a control circuit 24 for controlling these according to a plurality of external signals.
[0051]
The refresh counter 21 holds an address of a memory cell section to be refreshed next in the auto refresh and the self refresh, outputs the address to the memory cell section as a refresh address, and outputs the refresh address to the conversion circuit 23. After the refresh operation is completed, the refresh address held by the control circuit 15 is counted up in response to the update signal from the control circuit 15.
[0052]
The output buffer 22 receives the divided refresh address from the conversion circuit 23, receives the shift signal of the control circuit 24, and outputs it from a plurality of output terminals 25 to the outside.
[0053]
The conversion circuit 23 receives the n-bit refresh address from the refresh counter 21, divides it into a plurality of groups so as to match the bit width m of the output buffer 22, receives a transfer signal from the control circuit 24, and outputs it. Output to the buffer 22. The bit width n of the refresh address and the bit width m of the output buffer 22 differ depending on the product. For example, if the output DQ has a data width of 16 bits, that is, a so-called 16-bit product and m is n or more, the conversion circuit 23 Can be omitted.
[0054]
The control circuit 24 has a clock input terminal 26, a plurality of command input terminals 27, and a plurality of subcommand input terminals 28. The clock signal CLK input from the clock input terminal 26 is used for synchronizing the entire semiconductor device. Signals input from command input terminal 27 and subcommand input terminal 28 define the operation of the semiconductor device according to the combination.
[0055]
For example, as in the first embodiment, / RAS, / CAS, and / WE are used as command input signals, and BS0 and BS1 are used as subcommand input signals.
[0056]
The control circuit 24 generates and supplies necessary control signals to each circuit block of the semiconductor device including the refresh counter 21, the output buffer 22, and the conversion circuit 23 according to these input signals.
[0057]
Here, only the necessary circuit blocks and input signals around the refresh counter are shown.
[0058]
FIG. 2B is an input waveform diagram that defines auto-refresh in the second embodiment according to the present invention. In the semiconductor device according to the second embodiment, a subcommand for outputting a refresh address is additionally defined in an auto-refresh command, and the control around the refresh counter is changed accordingly.
[0059]
First, at the rising edge of CLK, / RAS, / CAS, / WE, BS0, and BS1 are taken in. If these are "0", "0", "1", "0", and "1", respectively, At the same time as the auto-refresh operation is started, the refresh address is output.
[0060]
Since the auto-refresh operation is performed in the same manner as in the first embodiment, the description is omitted here.
[0061]
On the other hand, the output of the refresh address is started by the transfer signal of the control circuit 24, and in response thereto, the refresh address is divided by the conversion circuit 23 into a plurality of data groups. Specifically, a parallel-serial conversion circuit or the like is used. For example, in a 4-bank 256-Mbit synchronous DRAM product having an output bit width of 8 bits, the refresh address is 13 bits (n = 13) and the bit width of the output buffer 22 is 8 bits (m = 8). Eight bit parallel-serial conversion circuits are arranged in parallel and divided into two 8-bit data groups. "0" or "1" is supplemented to the bit of the second data group for which the refresh address is insufficient.
[0062]
Next, in response to the shift signal of the control circuit 24 synchronized with the falling edge of the CLK, the output buffer 22 sequentially outputs the divided refresh addresses from the output terminal 25.
[0063]
According to the second embodiment, the refresh address held by the refresh counter 21 can be output at any time, so that a memory map for reading and writing all cell data can be obtained and the auto-refresh and self-refresh operations can be performed. The defective address can be confirmed by the output DQ from the output terminal 25, and a dramatic improvement in efficiency in evaluation and failure analysis can be realized.
[0064]
In the second embodiment, the conversion circuit 23 is used to adjust the refresh address to the bit width m of the output DQ. However, the bit width m of the output DQ is equal to the bit width of the refresh address as in a so-called 16-bit product. If it is larger than n, the refresh address can be output at once without using the conversion circuit 23.
[0065]
(Third embodiment)
FIG. 3 is a block diagram showing a configuration of an address control circuit of a semiconductor device according to a third embodiment of the present invention, and an input waveform diagram thereof.
[0066]
First, a circuit block diagram around the refresh counter will be described. As shown in FIG. 3A, the semiconductor device according to the third embodiment includes a refresh counter 31 for holding a refresh address, an address buffer 32 for taking in and holding an external address, and selecting a refresh address or an external address to select an internal address bus. A switching circuit 34 for outputting data to the outside 33; an output buffer 35 for outputting data to the outside; a conversion circuit 36 for dividing the refresh address from the refresh counter 31 into a plurality of data groups; and a control circuit for controlling these according to a plurality of external signals. Has 37.
[0067]
The refresh counter 31 holds the address of the memory cell section to be refreshed next in the auto refresh and the self refresh, and outputs this to the switching circuit 34 as a refresh address. Further, in response to a setting signal from the control circuit 37, an external address is received from the address buffer 32, and this is reset as a refresh address. Further, after the refresh operation is completed, the held refresh address is counted up in response to the update signal from the control circuit 37.
[0068]
The address buffer 32 has a plurality of address input terminals 38, receives an input signal from the control circuit 37, receives an input signal Add of the address input terminal 38, and holds this as an external address. At the same time, the external address is output to the switching circuit 34.
[0069]
Further, the address buffer 32 receives the setting signal from the control circuit 37 and outputs the held external address to the refresh counter 31 via the signal line 32A.
[0070]
The switching circuit 34 receives a switching signal from the control circuit 37, selects one of the refresh address and the external address, and outputs this to the internal address bus 33 as an internal address.
[0071]
The output buffer 35 receives the refresh address divided by the conversion circuit 34, receives the shift signal from the control circuit 37, and outputs this from a plurality of output terminals 39 to the outside.
[0072]
The conversion circuit 36 receives the refresh address from the refresh counter 31, divides it into a plurality of data groups so as to match the bit width m of the output buffer 35, receives a transfer signal from the control circuit 37, and Output to As in the second embodiment, when m is n or more in a so-called 16-bit product or the like, the conversion circuit 36 can be omitted.
[0073]
The control circuit 37 has a clock input terminal 40, a plurality of command input terminals 41, and a plurality of subcommand input terminals. Clock signal CLK input from clock input terminal 40 is used for synchronizing the entire semiconductor device. The signals input from the command input terminal 41 and the subcommand input terminal 42 define the operation of the semiconductor device according to the combination.
[0074]
For example, as in the first embodiment, / RAS, / CAS, and / WE are used as command input signals, and BS0 and BS1 are used as subcommand input signals.
[0075]
The control circuit 37 generates a control signal necessary for each circuit block of the semiconductor device including the refresh counter 31, the address buffer 32, the switching circuit 34, the output buffer 35, and the conversion circuit 36 in accordance with these input signals. Supply.
[0076]
Here, only the necessary circuit blocks and input signals around the refresh counter are shown.
[0077]
FIG. 3 (b) is an input waveform diagram defining addressing auto refresh in the third embodiment according to the present invention. In the semiconductor device according to the third embodiment, a subcommand for simultaneously setting a refresh counter and outputting a refresh address is additionally defined in an auto-refresh command, and the control around the refresh counter is changed accordingly.
[0078]
First, at the rising edge of CLK, / RAS, / CAS, / WE, BS0, and BS1 are fetched. If these are "0", "0", "1", "1", and "1", respectively, The refresh address is output simultaneously with the start of the designated auto refresh operation.
[0079]
At this time, Add from the address input terminal 38 is taken in at the same time and held in the address buffer 32 as an external address.
[0080]
The addressing auto-refresh operation is performed in the same manner as in the first embodiment. That is, the control circuit 37 first outputs a setting signal to the address buffer 32 and the refresh counter 31, and outputs the setting signal to the refresh counter 31 via the signal line 32A in order to set an external address of the address buffer 32 as a refresh address. Next, a switching signal is output to the switching circuit 34 to output the set refresh address of the refresh counter 31 to the internal address bus 33.
[0081]
Thereafter, similarly to the auto-refresh operation of the first embodiment, a read operation and a precharge operation are internally performed, and finally, the refresh counter 31 is counted up to complete the addressing auto-refresh.
[0082]
On the other hand, the output of the refresh address is performed in the same manner as in the second embodiment. That is, the control circuit 37 first outputs a transfer signal to the conversion circuit 36. In response, the conversion circuit 36 divides the n-bit refresh address from the refresh counter 31 into a plurality of groups and outputs the group. A specific method is the same as in the second embodiment, and a description thereof will be omitted.
[0083]
Next, in response to the shift signal of the control circuit 37 synchronized with the fall of CLK, the output buffer 35 sequentially outputs the divided refresh addresses from the output terminal 39.
[0084]
According to the third embodiment, the setting of the refresh address in the refresh counter and the output of the refresh address can be performed by one command, so that a dramatic improvement in evaluation and failure analysis can be realized.
[0085]
In the description of the first to third embodiments, the setting and output of the refresh address are performed simultaneously with the conventional auto refresh operation. However, the present invention is not limited to this. Settings and outputs may be defined as a single command.
[0086]
In addition, a conventional synchronous DRAM auto-refresh command is used as a command input, and BS0 and BS1, which are not used in the auto-refresh, are used as subcommand inputs. However, the present invention is not limited to this. Other inputs may be combined or new inputs may be defined.
[0087]
Further, in order to maintain compatibility with the specification of the conventional synchronous DRAM, the conventional command definition and the command definition of the present invention can be selected by using a mode register set command immediately after turning on the power. Good.
[0088]
【The invention's effect】
As described above, according to the present invention, an arbitrary address can be set in the refresh counter, and the refresh address held by the refresh counter can be arbitrarily read. A highly reliable semiconductor device can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an address control circuit of a semiconductor device according to a first embodiment of the present invention, and an input waveform diagram thereof.
FIG. 2 is a block diagram showing a configuration of an address control circuit of a semiconductor device according to a second embodiment of the present invention, and an input waveform diagram thereof.
FIG. 3 is a block diagram showing a configuration of an address control circuit of a semiconductor device according to a third embodiment of the present invention, and an input waveform diagram thereof.
FIG. 4 is a block diagram showing a configuration of an address control circuit of a conventional semiconductor device, and an input waveform diagram showing an auto-refresh entry method.
[Explanation of symbols]
11, 21, 31 refresh counter
12, 32 address buffer
12A, 32A Signal line for address setting
13, 33 Internal address bus
14, 34 switching circuit
15, 24, 37 control circuit
16, 38 Address input terminal
17, 26, 40 clock input terminals
18, 27, 41 Command input terminal
19, 28, 42 Subcommand input terminal
22, 35 output buffer
23, 36 conversion circuit
25, 39 output terminals

Claims (8)

A refresh counter for holding a refresh address for selecting one group of the memory cell unit divided into a plurality of groups;
An address buffer for holding an external address input from an address input terminal, a command input signal and a subcommand input signal are received, and the external address held in the address buffer is received based on the command input signal and the subcommand input signal. A control circuit for controlling a refresh address to be set in the refresh counter;
A semiconductor device comprising: A switching circuit that selects one of the address from the refresh counter or the address from the address buffer and outputs the selected address as an internal address;
Refresh means for refreshing one group of the memory cell unit selected according to the internal address;
When the external address is set in the refresh counter, the control circuit continuously controls the switching circuit to select the external address set in the refresh counter as a refresh address and output the selected external address as the internal address. The semiconductor device according to claim 1, wherein: A refresh counter for holding a refresh address for selecting one group of the memory cell unit divided into a plurality of groups;
An output buffer for holding output data;
A control circuit that receives a command input signal and a subcommand input signal, and controls the refresh address held in the refresh counter to be output to the outside via the output buffer based on the command signal and the subcommand signal;
A semiconductor device comprising: A conversion circuit that divides the refresh address into a plurality of data groups and reduces the bit width of the data group to at least the bit width of the output buffer is provided between the refresh counter and the output buffer. 4. The semiconductor device according to claim 3, A refresh counter for holding a refresh address for selecting one group of the memory cell unit divided into a plurality of groups;
An address buffer for holding an external address input from an address input terminal, an output buffer for holding output data,
A command input signal and a subcommand input signal are received, and based on the command signal and the subcommand signal, the external address held in the address buffer is set as a refresh address in the refresh counter, and the refresh counter is set in the refresh counter. A control circuit for controlling a refresh address to be output to the outside via the output buffer;
A semiconductor device comprising: A conversion circuit that divides the refresh address into a plurality of data groups and reduces the bit width of the data group to at least the bit width of the output buffer is provided between the refresh counter and the output buffer. 6. The semiconductor device according to claim 5, wherein A switching circuit that selects one of the address from the refresh counter or the address from the address buffer and outputs the selected address as an internal address;
Refresh means for refreshing one group of the memory cell unit selected according to the internal address;
The control circuit, when the external address is set as the refresh address in the refresh counter, continuously outputs the refresh address set in the refresh counter to the outside via the output buffer, and the switching circuit, 6. The semiconductor device according to claim 5, wherein control is performed such that a refresh address set in said refresh counter is selectively output as said internal address. 8. The semiconductor device according to claim 2, wherein the control circuit further has a function of updating the refresh counter after refreshing the memory cell unit using the refresh unit.

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