JPS61198814A - Trigger detection circuit - Google Patents

Abstract

PURPOSE:To minimize number of circuit components and to detect the sequence of a high speed input data by inputting an output of a shift register to an address input of the 2nd memory and outputting a trigger signal when the sequence of input data is coincident with a trigger map data. CONSTITUTION:An identification code whether an input data 20 is a trigger data or not is set to a memory 1. Output data 1A-1E of the memory 1 are inputted to shift registers 2-6 by an identification code in 5-bit corresponding to the input data 20 and shifted in order by using a clock signal delayed by a delay circuit 10. Data are set to the memories 7, 8 so that output data of the memories 7, 8 are logical 1 when the address is designated by the expected identification data. When the 5-bit identification codes are all expected identification codes at outputs 21-24 of the shift register, the output of the memories 7, 8 goes to logical 1, resulting that the output of an AND gate 9 is logical 1, logical 1 is outputted to a trigger output terminal 1 to detect the trigger data.

Description

DETAILED DESCRIPTION OF THE INVENTION ('a) Technical Field of the Invention The present invention relates to a trigger detection circuit composed of a memory and a shift register.

(b) Prior Art and Problems A protocol analyzer or the like may want to detect whether a received sequence of characters or symbols matches expected data.

An example of a conventional circuit in such a case is shown in FIG.

In FIG. 2, 101 is a buffer 1 memory for temporarily storing input data, 102 is a reference data memory for storing trigger data, and 103 is a CPU.

104 is a data memory that stores input data and trigger signals.

In the circuit shown in Figure 2, 8-bit parallel data is taken as one character, and a sequence of 10 characters, for example rABCDEF
If a trigger output is to be obtained when input data is input in the order GHIJJ, expected data rABCDEFGHIJJ is first set in the reference data memory 102 in advance.

Next, the input data is stored character by character in the buffer memory 101 (but the CPU 103 stores the input data character by character in the buffer memory 101).
1 has stored 10 characters, the character sequence in the buffer 1 memory 101 is compared with the character sequence in the reference data memory 102, and if they match, the CPU 1
03 outputs a trigger signal and stores the input data of the buffer memory 101 and the trigger signal in the data memory 104.

If the character sequences in the buffer memory 101 and the reference data memory 102 do not match as a result of the comparison, the input data stored in the buffer memory 101 is transferred to the data memory 1.
It will only be stored in 04.

Thereafter, each time one character of input data is input to the buffer memory 101, the CPU 103 compares and collates the character sequence with the reference data memory 102, and repeats the operation of storing data and trigger signals in the data memory 104.

In the conventional circuit example shown in FIG. 2, CPU 103 compares and matches character sequences. Therefore, the procedure and operation of comparison and verification are controlled by a program, and there is a problem that the program cannot process in time for high-speed input data.

In addition, in the example shown in FIG. 2, the trigger character sequence is one type of 10 characters, but if you increase the number of characters in the character sequence or want to detect a trigger with several types of character sequences, the load on the CPU 103 will increase. Furthermore, if the DON'T CARE bit is set in the data in the reference data memory 102, there is a problem that the CPU 103 will not be able to process high-speed signals.

(c) Object of the Invention The present invention provides a trigger detection circuit that can detect a high-speed sequence of input data while minimizing the number of circuit components.

(d) Examples of the invention A block diagram of an embodiment according to the present invention is shown in FIG.

In FIG. 1, 1 is a memory for code conversion, 2 to 6 are shift registers, 7 and 8 are memories for storing trigger map data,
9 is an AND gate, 10 is a delay circuit, and 11 is a trigger output terminal.

The clock signal 31 is synchronized with the input data 20 and is input to the delay circuit 10 . This delay circuit 10 includes a memory 1
This is to compensate for access time.

In the embodiment shown in FIG. 1, input data 20 is 8-bit parallel data and is input to the address input of memory 1.

An identification code is set in the memory 1 to determine whether the input data 20 is trigger data or not.

The output data IA-IE of the memory 1 is input to the shift registers 2 to 6 as a 5-bit identification code corresponding to the input data 20, and is sequentially shifted using a clock signal delayed by a delay circuit 10.

The shifted identification code outputs 21-24 of 5 bits each are input to the address input of the memory 7.8.

Data is preset in the memory 7.8 so that the output data of the memory 7.8 becomes "1" when addressed by the expected identification data.

In other words, when the 5-bit identification codes of the shift register outputs 21 to 24 are all the expected identification codes, the memory 7
．． The output of 8 becomes "1". As a result, the output of the AND gate 8 becomes "1", "1" is outputted to the trigger output terminal 11, and it is detected that it is trigger data.

Next, an example of the detailed explanatory diagram of FIG. 1 is shown in FIGS. 3 and 4, and the operation of the embodiment of the present invention will be explained.

In the embodiment shown in FIG. 1, 8-bit parallel data is used as input data, and shift registers 2 to 6 can be shifted by four stages, so that trigger detection can be performed using a sequence of up to four pieces of input data.

For example, if 8-bit input data 20 is (BC)H, (DE)H, (FO)H.

(11) If the bird wants to output a signal when hexadecimal data is input in the order of H, data is set in the memory 1 as shown in FIG.

In other words, the identification code (00001)2 is assigned to trigger data (11)H, and (00010) is assigned to (BC)H.
)2, (DE)H is assigned (00011)2, and (FO)H is assigned (00100)2.

In the example shown in FIG. 3, identification code (00000) 2 is assigned to data other than trigger data.

Data is set in the memory 7 as shown in FIG.

Address input 21 of memory 7 is (00001)2 and remaining address input 22 is (0
0100) The data at the address 2 is set to "1" and all others are set to "0".

That is, in the memory 7, "1" is set at the addresses specified by the identification codes of the last two trigger data (FO)H and (11)H of the trigger sequence.

Thereafter, data is similarly set in the memory 8 as shown in FIG. Here, along with input 20, clock signal 3
When 1 is input, the identification code for the input data 20 is output from the memory 1.

Each bit output IA to IE of the identification code is input to shift registers 2 to 6, respectively, and shifted by a clock signal passed through a withdrawal circuit 10.

This clock signal is input once for each data input.

The same operation is performed for the subsequent input data, and the name identification codes are sequentially changed to 7 Futrenosk 2 to 6 without corresponding to the input data.
The address of the memory 7.8 is determined as t.

Input data is (BC)Hl (DE)H.

When input in the order of (FO)H and (11)H, the trigger data (B
C) The identification code (00010) 2 of H is output and input to address inputs A9 to A5 of the memory 8.

On the other hand, the identification code (00011) 2 of the trigger data (DE) H is output to the outputs 23 of the shift registers 2 to 6, and is input to the address inputs A4 to AO of the memory 8.

As a result, address inputs A9 to AO of memory 8 are (00
01000011)2=(043) Address H is designated and "1" is output to the data output 8A of the memory 8 as shown in FIG.

Similarly, since an address corresponding to the trigger data as shown in FIG. 7 is specified for the memory 7, the data output cuff A also outputs "1".

The output of the AND gate 9 becomes "1" under the condition that the output of the memory 7.8 becomes "1", that is, when the input data and its sequence match the trigger data, and the output of the trigger output terminal 1 becomes "1".
A trigger signal is output from 1.

If the input data is different from the trigger data or the sequence of the input data is different, the output cuff A of memory 7.8
, 8A becomes "0", the trigger condition is not satisfied, and the trigger output terminal 11 becomes "0".

In the embodiment shown in Fig. 1, the identification code set in memory 1 is 5 bits, so it is possible to set up to 2'' = 32 types of input data.If you want to increase the types of trigger data, change the number of bits of the identification code. If you need fewer types of trigger data, you can reduce the number of bits in the identification code.

In addition, in the embodiment shown in Fig. 1, up to four input data sequences can be set, but if you want to increase the number to eight, change shift registers 2 to 6 from 4 stages to 8 stages, and do the same as 7 and 8. This can be easily achieved by adding memory elements.

Further, in the embodiment shown in FIG. 1, a trigger can be detected using one type of sequence, but it is also possible to easily detect several types of sequences simultaneously and extract a trigger signal.

For example, the memory 7.8 in the embodiment of FIG.
This is an example using a bit memory, but if you use an IK word x 4 bit memory in memory 7.8 and use four gate circuits similar to AND gate 9, four types of sequences can be detected at the same time. I can do it.

(e) Effects of the Invention According to the present invention, by using a combination of a memory and a shift register, the sequence of even high-speed input data can be checked against trigger data, and the trigger can output a signal.

Another advantage is that the number of memories and shift registers can be reduced by minimizing the types of trigger data and the number of sequences.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment according to the present invention, and FIG. 2 is a circuit diagram of an embodiment according to the present invention.
A diagram showing an example of a conventional circuit; FIGS. 3 to 7 are explanatory diagrams of FIG. 1. 1...Memory, 2-6...Shift register, 7...Memory, 8...Memory,
9...AND gate, 10...Delay circuit, 11...Trigger output terminal, 20...
- Input data, 21 to 24... Output of shift register, 31... Clock signal. Agent Patent Attorney Kinji Omata No. 1 Figure 2 + Il Figure 3 Figure 4 Figure S
Book Figure 6 Figure 7

Claims (1)

[Scope of Claims] 1. A first memory that converts input data into a code, a shift register that shifts the conversion code of the first memory, and a second memory that stores a trigger map. A trigger detection circuit, characterized in that an output is input to an address input of a second memory, and a trigger signal is output when the sequence of the input data matches the trigger map data.