JPS5949042A - Character detecting system of circuit adaptor - Google Patents

Abstract

PURPOSE:To reduce the capacity of a memory which is needed for identification of control characters and at the same time to decrease the time needed for discrimination of control characters, by distributing the individual bits forming a transmission control character to a circuit adaptor at word positions different in address corresponding to those individual bit positions. CONSTITUTION:The control character codes incidental to the transmission control procedures set with each circuit are stored in a control character code memory 5 at a circuit corresponding part 3 from a memory 16 for control program when an initial state is indicated to a communication controller by application of a power supply or resetting, etc. The control character code is written to the memory 5 via a control character code writing control circuit 4. As shown by the 3rd example, the control character is stored in the memory 5 in the word direction of the memory. That is, the data of the same bit position are sotred in the bit direction within the same word of the memory 5 for different control characters. If a bit holding circuit is set at logic ''1'' showing detection of some control character through a control character detecting circuit 7, an interruption is executed to a processing part 1 for a character processing request.

Description

Detailed Description of the Invention: Technical Field of the Invention The present invention relates to a communication control device, and particularly includes a main processing section, the above-mentioned unique section, and a line adapter, the line adapter being a main processing section. In a communication control device that is connected to the control bus and the data bus of the FM section and controls data transmission with the line, the line adapter is provided with a method that can efficiently detect transmission control characters. Regarding the method.

(b) Problems with the prior art As a conventional method for detecting transmission control characters, identification codes of transmission control characters and general characters stored in memory are
Instead of reading out the characters assembled from data as addresses, a method was adopted that discriminated and detected transmission control characters. According to this conventional method, the memory for storing the identification code required the same amount of space as the number of bit combinations that make up one character. In addition, after assembling the received data into one character, the memory is read out and it is determined whether or not it is a control character, which requires a certain amount of time after assembling one character.

(C) Object of the Invention An object of the present invention is to provide a system that reduces the size of the memory required to identify control characters and reduces the time required to identify control characters.

2) Structure of the Invention In order to achieve the above object, the Kine Rihiki includes a main processing unit, the above-mentioned 1 affected area, and a line adapter, where the cough line adapter is the main part. JM to data bus
In a communication control device configured to perform data transmission with an fA line, each bit constituting one transmission control character is assigned to a different address corresponding to the bit position in the line adapter. At the same time, the constituent bits of each transmission control character are placed in the same bit direction position within each word, and each bit of received character data is placed in the same bit position of each transmission control character. A memory configured so that data can be read simultaneously and the number of characters M of data received from the line.
After establishment, each time one bit of received data is received, the contents of the above memory are read at the address corresponding to the bit position of the received bit, and one bit of all read transmission control characters is compared with one bit of received data. and a pit comparison result holding means for holding the comparison result, and at the time of completion of receiving one character, it identifies whether or not the received character is a transmission control character based on the contents of the bit comparison result holding means. If the character is a transmission control character, it is characterized in that it is configured to determine whether the character is duplicated.

(e) Embodiment of the invention Figure 1 is a block diagram of a communication control device according to an embodiment of the present invention, Figure 2 is a block diagram of a transmission control character detection mechanism according to an embodiment of the present invention, and Figure 3 is a block diagram of a transmission control character detection mechanism according to an embodiment of the present invention. FIG. 3 is a diagram showing an example of the contents of a transmission control character code memory.

In the figure, 1 is the main processing section, 2 is the main storage section, 3 is the line corresponding section, 4 is the control character code writing control circuit, 5 is the control character code memory, 6 is the gun output register, and 7 is the ff1t control character output. 8 is a received character assembly control circuit, 9 is a character buffer circuit, lo is a bit count circuit, 11 is a memory address control circuit, 12 is a modulation/demodulation device, 13 is a data bus, 14 is an address bus, 15 is a control bus , 16 & control program memory 1.17-1 to 1
7-n is an exclusive OR circuit, 18-1 to l (3-n is an AND circuit, 19-1 to 19-n are flip-flop circuits, 20-1 to 20-n are an AND circuit, and 21 is a register. 22 is an OR circuit, 23 is an inverter circuit, 24 is a register circuit, and 25 is an inverter circuit.

The operation of the embodiment is as follows.

First, when the communication control device instructs the device to return to its initial state by powering on or resetting, the control character code corresponding to the transmission control procedure set for each line is transferred from the control program memory 16 to the line corresponding unit 3. The control character code is stored in the control character code memory 5. The control character code is written into the control character code memory 5 via the control character code writing control circuit 4. Control characters are stored in the control character code memory 5 in the word direction of the memory, as shown in the third example. Data of the same pitch H[ for each different control character is stored in the bit direction within the same word of the memory.

When detecting a control character during data reception, the received character assembly control circuit 8 detects a synchronous character, resets the bit count circuit 10 to set the counter to an initial value, and also sets the address of the memory address control circuit 11 to the initial address. The control character code memory 5 is read at the address specified by the memory address control circuit 11 and set in the read register 6.

In parallel with the operation of assembling the received Gi data transferred from the flat Ti tone device 12 into a character in the received character/text control circuit 8, the received data is read out and set in the read register 6 in the control character detection circuit 7 every time one pit is received. The n-th bit of each control character is compared, and if there is a difference, that fact is stored. 1
When the characters are received, the characters assembled by the received character assembly control circuit 8 are transferred to the character buffer circuit 9 and reception is stopped. In this 11Jl/control character detection circuit 7, if the bit holding circuit indicating the detection of some control character is logic -1'', a character processing request is interrupted to the processing unit l.If the bit holding circuit indicating the detection of a control character is held. All circuits are logic PU'''0
”, a request is made to transfer the characters in the character buffer circuit 9 to the random access memory 2. It is shown below.

After synchronization is established, when the first bit is received, exclusive OR circuits 17-1 to 17-n determine whether or not they match the first bit of each control character read out to read register 6. . If they do not match, the fact is stored in the inputs of the AND circuits 18-1 to 18-n and the flip-flop circuits 19-1 to 19-n following the logic "1" signal. Since logic "'l" is set on the positive side of flip-flop circuits 19-1 to 19-nFJO when synchronization is established, in case of mismatch, the logic is inverted to logic 1°0". In this case, the contents of the flip-flop circuits do not change.While the received signal (RD) is being received for one character, the above comparison and judgment are performed continuously, and when the reception of one character is completed, the contents of the flip-flop circuits 19-1 to 19-1 are changed. The content of 19-I'm, that is, information on whether or not a control character is detected, is sent to the AND circuit 20-1.
.about.20-n to the register circuit 21.

At this time, as a matter of course, only the flip-flop circuit corresponding to the reception control character is at logic "1". If the output of the OR circuit 22 is logic "l", it is determined that a special character has been detected and is sent as an interrupt signal to the RQ multiplier signal processing unit l to request character processing. At this time, what kind of control character has been detected can be determined from the CCHOA-CCHN signals.

If the output of the OR circuit 22 is logic ``0'', it is regarded as a general character, and the inno (-event circuit 25 also requests to transfer the inverted character directly to the random access memory as an MRQ signal).

The DTCT signal is a shift signal to the register circuit 21 and a flip-flop circuit 19- when synchronization is established and after receiving one character.
Each character receiver from 1 to 19-n (used for initial setting before Fj).

The register circuit 24 is for storing and controlling the board sides of different control characters depending on the transmission control procedure. When the convex character pattern is treated as a control character, the corresponding bit stores logic TPA"'1", and when it is treated as a non-control character, the corresponding bit stores Lλ logic "o",
AND circuit 20-1~'IQ7nf! I control flJ.

(F) Effects of the Invention According to the present invention, since the processing request to the software is not made to perform the process of determining whether or not the character is a control character every time a character is assembled, a general character is If it is a control character, the data can be immediately transferred to the storage device, and if it is a control character, the control character necessary for processing can be performed immediately because the control character is known at the time of reception. and has the effect of improving transfer ability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a control device according to an embodiment of the present invention, FIG. 2 is a block diagram of a control character detection mechanism of an embodiment of the present invention, and FIG. 3 is a block diagram of a control character detection mechanism according to an embodiment of the present invention. FIG. 3 is a diagram showing an example of the contents of a code memory. In the figure, l is the main processing section, 2 is the main storage section, 3 is the line corresponding section, 4 is the control character code writing control circuit, 5 is the control character code memory, 6 is the indulgence register, 7ii is the control character detection circuit, 8 1 is a received character assembly control circuit, 9 is a character buffer circuit, 10 is a bit count circuit, 11 is a memory address control circuit, 12 is a modulation/demodulation device, 13 is a data bus,
14 is address bus, 1stri control bus%1
6idf [i control program memory, 17-1 to 17
-n is an exclusive OR circuit, 18-1 to 18-n are AND circuits, 19-1 to 19-n are free-lag frog circuits, 2'
0-1 to 20-n are AND circuits, 21 is a register circuit,
22 is an OR circuit, 23 is an inverter circuit, 24 is a register circuit M, and 25r=jf sober-41 circuit. (1) 4t4 #fI' (ZTJ sentence 1zS'lHθθθ
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Claims (1)

[Scope of Claims] (1) A main processing unit, etc., includes a main storage unit and a line adapter, and the line adapter is connected to a control bus of the main processing unit and a data bus of the main storage unit, and the line adapter is connected to a control bus of the main processing unit and a data bus of the main storage unit, and the line adapter is connected to a control bus of the main processing unit and a data bus of the main storage unit, and the line adapter is connected to a control bus of the main processing unit and a data bus of the main storage unit. Control transmission 1
1, the line adapter is configured to cause the line adapter to place each bit constituting one transmission control character in a word position of a different address corresponding to the bit position, and for each transmission control character. The memory is configured such that the tN bit is arranged at the same bit direction position in each word, and the bit data at the same bit position of each transmission control character is read out simultaneously every time one bit of received character data is received. Then, every time one bit of received data is received at the character synchronization of the received data from the line i1g, the contents of the above memory are read out with the address corresponding to the bit position of the received bit, and all transmission control outputted from tt is executed. It is equipped with a bit comparison result holding means for holding the comparison result of 1 bit of character data and 1 bit of the Seven Immortals, and 1 character reception (at the time of completion of N, based on the contents of the bit comparison result holding means) In addition to identifying whether or not the received character is a transmission control character,
A character detection method for a circuit adapter, characterized in that, in the case of characters, the type thereof is determined. (2) The line according to claim (I), characterized in that, when the received character is a general character, the received character is transferred to the main storage unit without interrupting the main processing J. Adapter character detection method. (3) At the time of initial setting of the communication control device, the contents of all transmission control characters determined by the transmission control procedure are stored in the corresponding areas of the memory. Patent B'lW sought range No. 0 or No. (
Line adapter character detection method described in section 2). (4) The comparison result holding means is turned on before receiving one character, and then turned off when the bit read from the f memory and the received data bit do not match. 1. A character transfer system for a line adapter as set forth in any one of Items (1) to (3) of the Nik patent application, characterized in that the line adapter is configured to be compatible with the following.