JPH01140358A - Circuit for detecting write error on random access memory - Google Patents

Abstract

PURPOSE:To prevent a state where error data is stored in a RAM from being continued by detecting a write error by comparing input data to the RAM with output data from the RAM at the time of writing data on the RAM. CONSTITUTION:The title circuit is constituted so that the noncoincidence of the data can be detected immediately at a comparator 3 after write by using the coincidence between the input data and the output data of the RAM 1 at the time of writing the data, and an error detection signal ERROR is outputted from a holding circuit 4. Thus, since the write error of the RAM 1 can be detected by the comparator 3 at the time of writing the data on the RAM 1, it is not necessary to store the error data in the RAM 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to random access memory (hereinafter referred to as RA).
The present invention relates to a write error detection circuit (referred to as M).

[Conventional technology]

FIG. 3 is a block diagram showing an example of a conventional RAM write error detection circuit. In the figure, 1 is a RAM, 4 is a holding circuit, 5 is a parity pit generation stage addition circuit, and 6 is a parity check circuit. .

Next, the operation will be explained. n-bit input data (D
In) through the parity bit generation/addition circuit 5, R
Write to AM1. As a result, (n+i) bit data to which the harrity bit has been added is written into the RAM1. Next, when the chip enable signal (CFJ) goes low, the contents written at the address (Am) at that time are transferred to the data output terminal (Don) of RAM1.
-+-1) and an error exists in the output data (Don), an error detection signal is generated by the parity check circuit 6. Furthermore, the chip enable signal (C
At the time when E) returns to High, the error detection signal is held in the holding circuit 4, and the error detection signal (ERaou
) is output as

Note that once an error is detected, the error detection signal (ERROR) remains held unless a reset (R8T) is applied.

[Problem that the invention seeks to solve]

Since the conventional RAM write error detection circuit is configured as described above, there is a problem that a write error cannot be detected at the time of writing, and erroneous data must be stored in the RAM. Also, to handle n-bit data (n
There were problems such as the need for +1) bit RAM.

This invention was made to solve the above-mentioned problems, and provides a RAM write error detection circuit that can detect write errors during writing and can use n-bit RAM to handle n-bit data. The purpose is to

[Means for solving problems]

The RAM write error detection circuit according to the present invention utilizes the fact that the input data and output data of the RAM match at the time of writing, and immediately after writing the data mismatch is detected by the comparator circuit, and the error detection signal is sent from the holding circuit. It is designed to output .

[For production]

The comparator circuit in this invention detects one write to the RAM at the time of writing to the RAM.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is an n-bit RAM, 2 is a holding timing generation circuit that outputs a write end signal using the chip enable signal (CE) and write enable signal (wg) input to RAM1 as input signals, and 3 is an n-bit RAM. a comparator circuit that uses the input data (DIn) to be input and the output data (DOn) output from the RAM 1 as input signals, compares them, and outputs a mismatch signal when they do not match; 4;
uses the mismatch signal output from the comparator circuit 3 and the write end signal output from the hold timing generation circuit 2 as input signals, and outputs and holds an error detection signal (anion) if the input and output data do not match at the end of writing. This is a holding circuit.

FIG. 2 is a time chart showing a time chart when writing to the RAM 1 shown in FIG.

Next, the operation shown in FIG. 1 will be explained with reference to FIG.

When the write destination address (Am2) is designated at time (tl) and the chip enable signal (CE) is set low at time (t2), the contents of address (Am2) are output at time (1++α). Then, when the write enable signal (WE) is made low at time (tS), the data (Dn 1 ) input at time (is+β) is output.

After that, input data (Dn 2 ) at time (111)
When the output data is changed to (tII+γ), the output data becomes (
Dn2). Furthermore, at time (t5), the write enable signal (WE) is returned to high, and data (DBP) is written to the address (Amz). At this time, R
If the input/output data of the AM10 do not match, a mismatch signal is output from the comparator circuit 3, so this mismatch signal is held by the holding circuit 4 and output as an error detection signal (ERROR). Also, if an error is detected, it will be reset) (
Unless R8'r) is applied, the error detection signal (ERROR
) remains retained.

Note that α, β, and γ in the text represent various delay times of the RAM1.

Further, in the above embodiment, the chip enable signal (CE) and write enable signal 6t) are both negative logic, but one or both may be positive logic, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the invention, when writing to the RAM, the input data to the RAM and the output data from the RAM are compared by the comparator circuit to detect a writing error. Incorrect data, such as writing it multiple times,
It is possible to prevent the state stored in AMK' from continuing.

Further, an n-bit RAM can be used to handle n-bit data, and a parity pit generation/addition circuit and a check circuit are not required, so the circuit size can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a RAM write error detection circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a RAM write error detection circuit according to an embodiment of the present invention.
FIG. 3 is a block diagram showing a conventional RAM write error detection circuit. 1 is a RAM, 2 is a holding timing generation circuit, 3 is a comparison circuit, and 4 is a holding circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation (2 others) 1: RAM 2.
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Claims (1)

[Claims] In a random access memory write error detection circuit that detects a write error in a random access memory, the chip enable signal and write enable signal input to the random access memory are used as input signals to recognize the end of writing, and perform the write operation. a holding timing generation circuit that outputs an end signal, input data input to the random access memory and the random access memory;
a comparison circuit that uses output data output from a memory as an input signal and compares them and outputs a mismatch signal when they do not match; and the write that outputs the mismatch signal output from the comparison circuit and the hold timing generation circuit. A random access memory write error detection circuit comprising a holding circuit which uses an end signal as an input signal and outputs and holds an error detection signal if input and output data do not match at the end of writing.