JPS60114052A - Device for comparative decision of data - Google Patents

Abstract

PURPOSE:To enable arbitrary setting of coincident data and decision of coincidence of bit levels and of several types of data by using comparative data stored in the first memory as address signals of the second memory, and by outputting coincident data pre-stored in the second memory. CONSTITUTION:A memory 2 stores comparative data, and is controlled by a counter output 47, write pulse signal 44 and output enable signal 46, and a buffer 3 inputs comparative data 32 in the memory 2. The output of a counter 5 is connected to an address line, and word data 51 indicating word orders which are decided after comparison. A memory 6 stores coincident and non-coincident data and outputs coincident data 61 with the data 32 and data 51 as address signals. An FF7 is set by a write pulse signal 42, decides data 61 by a clock 48, and when the signal becomes coincident ''0'' even once, the FF7 continues a reset condition until it is set next. The device thus can set the number of words and coincident data 61 for the data 51 arbitrarily.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention In data communications, etc., a synchronization signal is sent from the transmitting side, and the receiving side detects this to establish synchronization.

In this case, synchronization may be achieved on the receiving side as follows. That is, the receiving side has the same signal as that of Dohoshin 5 as λ-type data, and compares this reference data with the input data. When both match, the input data at that time is used as a synchronization signal.The present invention relates to a data comparison/judgment device used in such a case.

(b) Conventional technology and problems Conventional devices include Japanese Patent Laid-Open No. 1000/17/1983, etc. In the conventional device of Arka and Co., reference data and comparison data are stored in one memory and the data are compared. . For this reason,
There is a problem in that reference data is limited, and comparison based on bi-situ matching or comparison based on OR matching of several types of characters cannot be performed.

(c) Purpose of the Invention This invention stores comparison data in a first memory, uses this stored data as an address signal for a second memory, and compares data stored in advance in the second memory. It is an object of the present invention to provide a comparison/judgment device for data that has been used to output data, so that matching data can be arbitrarily set, and it is also possible to judge bit-level matching and matching of several types of data. shall be.

(d) Example of the invention #Ze 7 Spring In 1. y-) Su ψ 剌士 /It+ 小戊 Gwap sword 太平 Shown in 11-1.

In FIG. 1, 1 is a counter, 2 is a first memory, 3 is a buffer, 4 is a control circuit, 5 is a second counter, 6 is a second memory, and 7 is a flip-flop.

The counter 1 receives a counter clock 4 from the control circuit 4.
5 and outputs a calafta output 47 as an address signal for the first memory 2.

The first memory 2 is a memory for recording comparison data fα,
It is controlled by a counter mount 47 from the counter 1, a memory write pulse signal 44 from the control circuit 4, and an output enable signal 46, and inputs and outputs comparison data 32.

The buffer 73 is a buffer for inputting the comparison data 32 to the first memory 2, and becomes valid when writing to the first memory 2 is performed using the memory write pulse signal 44 from the control circuit 4.

The control circuit 4 includes a counter 1, a first memory 2 and a bar.
Nof 73 is controlled.

The counter 5 operates with a counter clock 48 and connects its output to the address line of the second memory 6. Then, word data 51 indicating the word order for comparison and determination is output.

The counter clock 48 is obtained by passing the output enable signal 46 and the clock signal 41 through a gate circuit.

A memory or a flip-flop may be used for the counter and counter 5.

The second memory 6 is a memory that stores matches and non-matches, and stores the comparison data 32 from the first memory 2 and the counter 5.
The word data 51 from .

The flip-flop 7 is set by the write pulse signal 42 and the match data 61 . is determined by the count clock 48, and if the discrepancy becomes "0" even once, the reset barking state continues until it is set next time.

In this embodiment, the matching data 61 is rlJ matching, “0
” is considered inconsistent.

Next, an example of the time chart of FIG. 1 is shown in FIG. 2.

Figure 2 (7) shows the ``2-turn signal 4'' that is manually input to the control circuit 4.
1 waveform, clock signal 41 controls the speed and control of the vehicle in FIG.

FIG. 2(a) shows the waveform of the write pulse signal 42 that is manually input to the control circuits 4 and 7 lip-flop 7. The write pulse signal 42 is used when loading the comparison data 32 into the first memory 2 or when starting the control circuit 4. This is a necessary signal in this case.

FIG. 2 (9) shows the waveform of the buffer enable signal 43 input from the control circuit 4 to the buffer 3. When the write pulse signal 42 enters the control circuit 4, the buffer 1 enable signal 43 in FIG. It becomes effective.

As a result, the data bus signal 31 passes through the buffer 3 and becomes comparison data 82, which is written tα in the memory 2 of jsl by the memory write pulse 44.

FIG. 2 (2) shows the waveform of the counter clock 450 input from the control circuit 4 to the counter 1, and the J counter clock 45 controls the output state of the comparison data 32. The waveform of the output enable signal 46 input to the first memory 2 indicates that the comparison data 32 is being output from the first memory 2 when the output enable signal 46 is logic "1".

The counter operates at the fall of the color/color clock 45, and counts up or down in order from the 1' address that stores the oldest comparison data. As a result, from memory 2 of fEl, comparison data 32 is stored in the oldest order.
Output.

FIG. 2 (power) shows the waveform of the counter clock 48 that is input from the control circuit 4 to the counter 5 and flip-flop 7.・Continuously determine inconsistencies.

FIG. 2(g) shows the word data 51 input from the counter 5 to the address line of the second memory 6, and FIG. 2(b) shows the address line from the first memory 2 to the second memory 6. This is comparison data 32 that is manually input.

Flute '21ffi (ke) flips from second memory 6 to 7
Matching data 61 input to 0 sub 7, matching data 61
are stored in advance in the second memory 6, and are output in order from the first word.

FIG. 2(1) shows the determination data 71 output from the flip 70 knob 7.

The flip-flop 7 receives the light pulse 42 in FIG. 2 (a).
The matching data 61 from the second memory 6 is determined continuously, and the determination data 71 in FIG.
Output.

The determination result is valid from the falling point of the output enable signal 46 in FIG. 2(E) to the next falling point of the write pulse signal 42 in FIG. 2(A).

Note that by increasing the output data of the second memory 6 and the number of flip-flops 7, the number of data to be compared can be increased.

The dotted line in FIG. 2 ( ]) indicates the case where the determination is rOJ due to mismatch.

Next, an example of the comparison data 32 and matching data 61 stored in the second memory 6 is shown in FIG.

In Figure 3, there are addresses from Ao to A6, but AQ=A
3 is used for comparison data 32, and A4 and A5 are used for 7-code data 51.

Additionally, ■0 is assigned to the matching data 61.

For example, the comparison data 32 for the 1st, 2nd, 3rd, and 4th words of the word data 51 is at the address Ao"
When rOJ , A+ ” rOJ , A2=“0” and A3=1, the matching data 61 is stored in the second memory 6 so as to be “1”. Then, the standard matching characters are ``8'', ``8'', ``8'', and r8J.
When the words are consecutive, the determination data 71 becomes "1", and otherwise becomes "0".

(e) Effects of the Invention According to this invention, the number n of words in the word data 51 and the number m of matching data 61 can be arbitrarily set, so matching or mismatching of n consecutive words can be expanded to the bit level. , m types of consecutive matches and mismatches can be detected.

[Brief explanation of drawings]

1 is a block diagram of an embodiment according to the present invention, FIG. 2 is a diagram showing an example of the time chart of FIG. 1, and FIG. 3 is a diagram showing comparison data 32 and matching data 61 stored in the second memory 6-. The figure which shows an example. 1... Counter, 2... First memory, 3... Bupts 7.4... Control circuit,
5...Counter, 6...Second memory, 7...Flip-flop, 31...Data bus signal, 32...Comparison data , 41...
... Ri1tsuk signal, 42. −・・・・Lightno(
signal, 43...Balance enable signal,
44... Memory write pulse signal, 45...
...Color/return clock, 46...Output enable signal, 47...Counter output, 48...
... Counter clock, 51 ... Word data, 61 ... Match data, 71 ... Judgment data. Agent Patent Attorney Kinji Komata

Claims (1)

[Claims] 1. A first memory that stores comparison data; a second memory that stores matching data and non-matching data and inputs the comparison data recorded in the first memory as an address signal; A data comparison/determination device comprising: a flip 70 tube for determining continuity between matching data and non-matching data.