JPH0265433A - Terminal control circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of a CPU at the terminal equipment side due to an erroneous select signal by sending an output decode signal to a terminal equipment side when a decoded signal to a command string given from a host is latched sequentially and when the command string set to a terminal equipment side in advance is decoded. CONSTITUTION:A decoder 11 outputting the 1st-3rd decode signals c-f in response to a command string given from a host CPU 1 and discrimination circuits 12-14 latching the decode signals c-f outputted from the said decoder 11 sequentially and sending an output decode signal alpha to a terminal side CPU 4 when the command string is coincident with the command string set in advance in the terminal side CPU 4, are provided to the title circuit. Thus, the effect due to an erroneous select signal or noise is excluded and malfunction of the terminal side CPU 4 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a terminal control circuit for accessing a terminal from a host using a specific command. The configuration shown in FIG. 2 is known. In FIG. 2, 1 is a CPU on the host side such as an exchange, 2 is a decoder connected to the address bus a of the CPU 1, and decodes and outputs a select signal.
3 is a decoder that decodes data on the data bus C from the CPU 1 based on the select signal S of the decoder 2;
4 is a CPU on the terminal side that is activated by the decode signal d given from the decoder 3;

In the above configuration, when the decoder 2 supplies the select signal S, the decoder 3 decodes the data on the data bus C supplied from the CPU 1, and outputs a code signal d unique to the data. This output decode signal d accesses 0PU4, and CPU4 comes to be controlled by CPU1.

Problems to be Solved by the Invention However, in the conventional configuration as described above, since the output decoded signal d from the decoder 3 is directly applied to the CPU 4 on the terminal side, the select signal may be erroneously transmitted or may be affected by noise. If the access is made in response to this request, there is a problem in that an incorrect control signal is given to the CPU 4 on the terminal side.

The present invention solves the conventional problems as described above.
It is an object of the present invention to provide a terminal control circuit that can prevent malfunction of a CPU on the terminal side due to an erroneous select signal.

Means for Solving the Problems In order to solve the above problems, the present invention provides a decoder that outputs a decoded signal according to a command sequence given from a host side, and a decoder that outputs a decoded signal outputted from this decoder.
@Next latch 5. The apparatus is equipped with a determination circuit section that sends an output decoded signal to the terminal side when the command sequence matches a command string set in advance on the terminal side.

Effects The present invention has the following effects due to the above configuration. That is, the decoding of the command string given from the host side is sequentially latched, and when the command string set in advance on the terminal side is decoded, the output is A decoded signal is sent to the terminal side.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a terminal control circuit in one embodiment of the present invention. In this embodiment, parts that are the same as those in the conventional example shown in FIG.

The terminal control circuit 1o includes a CPU 1, a decoder 2, and a CP
It is connected between U4. In FIG. 1, 11 is a decoder connected to CPU 1 and decoder 2;
13 is a launch circuit which inputs the first decoded signal e of the decoder 11, and 13 is the output of the latch circuit 12 and the decoder 11.
a latch circuit which receives as input the second decode signal f of 14;
is a latch circuit which receives the output of the latch circuit 13 and the third decode signal g of the decoder 11 as inputs.

In the above configuration, the decoder 11 is applied with the select signal S, and if the select signal is to decode the first decode signal e, the decoder 11 generates the first decode signal e. This first decode signal e is launched by the latch circuit 12. Subsequently, when the select signal to be outputted the second decode signal f is input to the decoder 11, the decoder 11 generates the second decode signal f,
This is applied to the latch circuit 13. The latch circuit 13 outputs the second decoded signal f latched by the latch circuit 14 only when a signal is applied from the latch circuit 12. Similarly, when the decoder 11 generates the third decode signal gt in response to the next select signal, the latch circuit 14 latches the third decode signal g only when there is an output signal from the latch circuit 13, and outputs the decode signal d. is sent to the CPU 4.

As described above, according to this embodiment, by accessing fixed data from the host side to the decoder 11 three times K, it is possible to output the output decode signal (control signal) d to the terminal side 0PU4. . Therefore, decoder 1
In contrast to 1, even if the select signal is affected by noise or the like, it does not affect the terminal side. Furthermore, since the terminal-side CPLI 4 is controlled by combining three individual pieces of data, it is possible to independently control a plurality of terminals by combining the data.

In the above embodiment, the command string is made up of three commands, but it is not limited to three and can be any number. In this case, it is only necessary to connect latch circuits corresponding to the number of commands in multiple stages.

Effects of the Invention As described above, according to the present invention, there is a decoder that outputs a decoded signal according to a command sequence given from the host side, and a decoded signal outputted from this decoder is sequentially latched and set in advance on the terminal side. Since the present invention is equipped with a judgment circuit section that sends an output decoded signal to the terminal side when the command sequence matches the specified command string, it is possible to eliminate the effects of errors in the select signal and noise, thereby preventing malfunctions. Can be done. Furthermore, by changing the combination of data, multiple terminals can be individually controlled.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a terminal control circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional terminal control circuit. 1... Host side CPIJ, 2.11... Decoder,
4...Terminal side CPU, 10-...Terminal control circuit, 1
2.13.14...Latch circuit.

Claims (1)

[Claims] A decoder outputs a decoded signal according to a command sequence given from the host side, and the decoded signal output from this decoder is sequentially latched, and when it matches the command sequence set in advance on the terminal side, it is sent to the terminal side. 1. A terminal control circuit comprising: a determination circuit section that sends out an output decoded signal.