JPH11296391A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid erroneous recognition by another command and to prevent the occurrence of a malfunction by execution an operation which is indicated by command data when received command data can be identified as the result of detection by means of a command detecting circuit. SOLUTION: M-bit command data C1, C2,... inputted from an external part are inputted to a command register 50 and held by a command register 50. M-bit command data consist of two parts, that is, a high-order L(L<M)-bit and a low-order N(N=M-L) bit, they are provided with (p) numbers of command data for indicating (p) kinds (p<2M) of different operations as a whole and whole high-order L-bits and the low-order N-bits in respective kinds of command data are different. Then, the command error detecting circuit 52 judges command data transmitted from the command register 50 and command data are transferred to a command decoder 64 unless an error is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which performs a predetermined operation according to command data input from the outside.

[0002]

2. Description of the Related Art A semiconductor memory device, for example, a flash memory usually performs an operation specified by command data in response to command data input from the outside.
The command data is output by, for example, an external control circuit. Command data is input in parallel via a command terminal, temporarily held by a command buffer or a command register provided inside the semiconductor memory device, and thereafter, the held command data is decoded by a command decoder or the like, and accordingly The generated control signals are output to predetermined circuits.

FIG. 7 is a block diagram showing an example of the configuration of a command data processing circuit. As shown, M-bit command data of, for example, C1, C2,..., CM is input to the command register 50 from the command terminal, and is temporarily held by the command register 50. The command data held in the command register 50 is sent to the command data 62.

The command decoder 62 performs a decoding process based on the input command data, generates a control signal for performing an instruction operation of the command data, and generates a memory cell array and its peripheral circuits such as a row decoder,
Output to a column decoder and sense amplifier. As described above, the semiconductor memory device can perform an operation such as writing, reading, or erasing specified by the command data according to the command data input from the outside.

[0005]

By the way, in the above-mentioned conventional semiconductor memory device, command data generated by an external control circuit is transferred to an input terminal of a command register via a transfer line such as a data bus. In the transfer line, one or more bits of the data of a plurality of bits constituting the command data may change due to the influence of noise or the like. In the command data example shown in FIG. 8, for example, the command data instructing the input of serial data is 80H (where H indicates hexadecimal). This is "10000000" in binary
Can be written as During the transfer from the external control circuit to the command register via the transfer line, due to the influence of noise, etc.
For example, when the most significant bit changes, the command data is changed to "00000000", that is, 00H.
As shown in the figure, since 00H is command data indicating the read mode (1), the memory side differs from the serial data input originally planned by the external control circuit according to the received command data 00H. The operation is performed.

When a bit change of command data having a plurality of bits occurs due to the influence of noise or the like, the command decoder becomes an indistinguishable code, or another command data different from the original command data. Will be recognized as Due to this bit change, an operation different from the operation instructed by the original command data is performed in the semiconductor memory device, so-called erroneous operation occurs, the intended result cannot be obtained, and in some cases, the storage data in the memory is destroyed. May be affected.

The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a command from being erroneously recognized by another command when a bit error occurs in command data due to the influence of noise or the like. Accordingly, it is an object of the present invention to provide a semiconductor memory device which can prevent malfunction from occurring and can simplify the configuration of the malfunction prevention circuit.

[0008]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises an externally input M
(M is an integer of 2 or more) A semiconductor memory device that performs an operation specified by the command data in accordance with the command data, and receives the M-bit command data to identify the received command data. A command detection circuit for detecting whether or not the command data is detected, and a control circuit for performing an operation specified by the command data when the received command data is identifiable as a result of the detection by the command detection circuit. The M-bit command data is composed of two parts, upper L (L <M) bits and lower N (N = ML) bits, and a total of p commands indicating different operations of p types (p <2 ^M ) , The upper L bits of each command data are all different, and the lower N bits of each command data are all different.

Further, the semiconductor memory device of the present invention performs an operation specified by the command data in response to M (M is an integer of 2 or more) bits of command data input from the outside. A command detection circuit that receives the M-bit command data and detects whether the received command data is identifiable; and if the received command data is identifiable as a result of the detection by the command detection circuit, And a control circuit for performing an operation specified by the command data. The M-bit command data includes upper L (2 ≦ L <M) bits and lower N
(N = M−L) bits, and has p command data instructing p kinds (p <2 ^M ) of different operations in total, and the upper L bits of each command data are Is set so that it does not match other command data when at least two bits of data do not change.

Further, the semiconductor memory device of the present invention performs an operation specified by the command data according to M (M is an integer of 2 or more) bits of command data input from the outside. A command detection circuit that receives the M-bit command data and detects whether the received command data is identifiable; and if the received command data is identifiable as a result of the detection by the command detection circuit, A control circuit for performing an operation specified by the command data. The M-bit command data includes lower N (2 ≦ N <M) bits and upper L
(L = M−N) bits, and has p command data for instructing p kinds (p <2 ^M ) of different operations in total, and the lower N bits of each command data are Is set so that it does not match other command data when at least two bits of data do not change.

Further, the semiconductor memory device of the present invention performs an operation specified by the command data in response to M (M is an integer of 2 or more) bits of command data input from the outside. A command detection circuit that receives the M-bit command data and detects whether the received command data is identifiable; and if the received command data is identifiable as a result of the detection by the command detection circuit, And a control circuit for performing an operation specified by the command data. The M-bit command data includes p command data that instruct p types (p <2 ^M ) of different operations in total. Each command data is set so as not to coincide with other command data when at least 2 bits of data do not change.

Further, in the present invention, preferably, the control circuit decodes the received command data and generates a control signal for performing an operation instructed by the command data according to a result of the decoding. And a command buffer for holding the command data. The M-bit command data is transferred from the external control circuit to the command buffer in series or in parallel.

According to the present invention, the semiconductor memory device performs an operation instructed by the command data from the external control circuit in response to the command data. The command data is set so as not to become another command data unless there is a bit change of at least two bits. For example, in the M-bit command data, a plurality (for example, p
Here, by using a data code of p <2 ^M ) as command data, if a bit change occurs only in either the upper bit or the lower bit, the command data does not become another command data. The occurrence of an error can be detected by a command detection circuit or the like, and erroneous recognition of command data can be avoided, thereby preventing a malfunction of the semiconductor memory device.

The upper L of M-bit command data
If at least two bits do not change in any of the bits or the lower N bits, the command is set so as not to be erroneously recognized by other command data. Accordingly, when a bit change of the command data occurs on the command data transfer line from the external control circuit to the semiconductor memory device due to the influence of noise or the like, the change of the bit data can be detected. Malfunction can be prevented. Further, a circuit for preventing a malfunction can be simplified.

[0015]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention. As shown, the semiconductor memory device of the present embodiment includes an input / output control circuit 10, an operation logic control circuit 20, a status register 30, an address register 40, a command register 50, a control circuit 60, a row address buffer 70, and a row address decoder. 80, memory cell array 90, high voltage generation circuit 100, R / B (Ready / Busy) circuit 110, column buffer 120, column decoder 13
0, a column register 140 and a sense amplifier 150.

In the semiconductor memory device of the present embodiment, command data from an external control circuit is input to a command register 50 under the control of the input / output control control circuit 10, and is temporarily held by the command register 50. The held command data is transferred to the control circuit 60, and the control circuit 60 is provided with, for example, a command decoder, the command data input by the command decoder is decoded, and a control signal corresponding thereto is generated,
Each functional circuit, for example, a load address coder 8
0, sent to the column decoder 130 and the sense amplifier 150.

Hereinafter, the configuration and function of each functional circuit of the semiconductor memory device shown in FIG. 1 will be briefly described. The input / output control circuit 10 controls input and output operations of an address, data, command data, and a status signal indicating a state of a memory. For example, under the control of the input / output control circuit 10, command data is input from a command input terminal and is temporarily stored in the command register 50. The command data held in the command register 50 is sent to the control circuit 60 and decoded by a command decoder provided in the control circuit 60, and a control signal corresponding to the command data is generated. Also, based on the control of the input / output control circuit 10, a row address and a column address are input via an address input terminal, and a row address buffer 70 is input via an address register 40, respectively.
And input to the column buffer 120. Further, the operations of inputting write data from the outside to the data register 140 and outputting read data from the data register 140 to the outside during writing and reading are performed under the control of the input / output control circuit 10.

The operation logic control circuit 20 controls the input / output control circuit 10 according to an external operation control signal. External operation control signals include a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal / RE, and a write inhibit signal / WP.

The status register 30 includes a control circuit 60
Holds the status signal indicating the operation state output by the input / output control circuit 1
Output to the outside based on 0 control. Address register 4
0 holds the input row address and column address under the control of the input / output control circuit 10, outputs the held row address to the row address buffer 70, and outputs the column address to the column buffer 120.

The command register 50 holds a command input under the control of the input / output control circuit 10 and outputs the held command to the control circuit 60. As described above, the control circuit 60 includes the command decoder, and the command decoder decodes the command data input from the command register 50,
Control signals for controlling the operations of the status register 30, the column decoder 130, the data register 140, and the sense amplifier 150 are generated according to the decoding result. Further, control circuit 60 outputs a control signal to R / B circuit 110 and high voltage generation circuit 100, respectively.

The row address buffer 70 holds the row address from the address register 40 and outputs it to the row address decoder 80. Row address decoder 80
Selects a specified word line among a plurality of word lines of the memory cell array 90 in accordance with an input row address, and applies an activation voltage to the selected word line. The activation voltage applied to the selected word line is, for example, a voltage generated by the high voltage generation circuit 100.

The memory cell array 90 is composed of a plurality of memory cells arranged in a matrix. The memory cells in each row are connected to the same word line, and the memory cells in each column are connected to the same bit line. Further, the word lines are connected to the row address decoder 80, and the bit lines are connected to the sense amplifier 150.

The column buffer 120 holds the column address from the address register 40 and outputs it to the column decoder 130. The column decoder 130 selects a designated bit line from a plurality of bit lines according to the input column address.

The data register 140 holds the write data input at the time of writing, and
Enter 0. At the time of reading, the data read by the sense amplifier 150 is held, and the held data is output to the outside.

The sense amplifier 150 reads the data stored in the selected memory cell according to the potential of the bit line selected at the time of reading, and outputs the data to the data register 140.
At the time of writing, the potential of the selected bit line is set according to the write data held in the data register 140, and the write data is written to the selected memory cell.

In the semiconductor memory device configured as described above, command data input from the outside is temporarily stored in the command register 50 and then sent to the control circuit 60. The control circuit 60 decodes the command data, generates control signals for controlling the operation specified by the command data, and outputs the control signals to predetermined functional circuits. For this reason, for example, the external control circuit that manages the memory can cause the semiconductor memory device to execute a predetermined operation through command data, thereby realizing data writing, reading, or erasing.

FIG. 2 is a block diagram showing the configuration of the command data processing circuit. Hereinafter, the flow of command data in the semiconductor memory device of the present embodiment will be described with reference to FIG. M-bit command data C1, C2,..., CM input from the outside via command terminals
Is input to the command register 50 and is held by the command register 50. Then, the command register 50
Is sent to the command error detection circuit 52.

The command error detection circuit 52 includes, for example,
The control circuit 60 shown in FIG.
It is provided in. The command error detection circuit 52 determines the command data sent from the command register 50, transfers the command data to the command decoder 64 when no error is detected, and notifies the command error when an error is detected. _Is output to the control circuit 60. When receiving the notification of the command error occurrence, the control circuit 60 performs processing such as outputting a signal for requesting command retransmission to the external control circuit.

When no error is detected in the command data, the command decoder 64 decodes the command data, generates a corresponding control signal, and outputs the control signal to the memory cell array and its peripheral circuits.

The configuration of command data output from the external control circuit and the command error detection operation in command error detection circuit 52 will be described below. Here, it is assumed that the command data from the external control circuit is 8 bits. In the present embodiment, when a method of setting 8-bit command data is determined, when a bit change occurs due to the influence of noise or the like during command data transfer, it can be detected, and malfunction of the semiconductor memory device due to erroneous recognition of a command is prevented. To prevent.

FIG. 3 shows an example of the command data. Here, the command data of 8 bits is divided into upper 4 bits and lower 4 bits, and the upper 4 bits and lower 4 bits of all the command data are set to be different. Thereby, for example, the command data “00H”
Only one of the upper 4 bits changes to "10H", that is, the binary number "000100" due to the influence of noise or the like.
When it changes to "00", the occurrence of a malfunction can be prevented without being erroneously recognized as the command data "1F".

FIG. 4 shows another example of the command data. In this example, when at least two bits of the upper four bits of the 8-bit command data do not change, the command data does not match other command data.
Command data is set. For example, command data “0XH” (X is an arbitrary 4-bit binary data, ie,
In the upper 4 bits of the hexadecimal data 0 to FH), only one bit changes, and “1X
When it changes to "H", the code "1XH" does not correspond to any of the other command data. Therefore, a bit change of only one bit does not cause erroneous recognition of the command and can prevent malfunction.

FIG. 5 shows an example of the set command data based on the same concept as the example of the command data shown in FIG. As shown in the figure, in the 8-bit command data, the command data is set so that when at least 2 bits of the lower 4 bits do not change, the command data does not coincide with other command data. For example, when only one bit changes in the lower 4 bits of the command data “X0H” and changes to the code “X1H”, the code “X1H” does not correspond to any of the other command data. With the change, erroneous recognition of a command does not occur and occurrence of a malfunction can be prevented.

FIG. 6 shows an example of the command data when the bit change is taken into consideration for the 8-bit command data as a whole. That is, in the 8-bit command data, the command data is set so that when at least two bits do not change, the command data does not match other command data. For example, in the lower 4 bits of the command data “00H”, only one bit changes, and the code “01H”
In this case, the code "01H" does not correspond to any of the other command data, so that a bit change of only one bit does not cause erroneous recognition of the command, thereby preventing the occurrence of a malfunction.

In this embodiment, a plurality of command data are set in advance by any one of the setting methods shown in FIGS.
Various operations of the semiconductor memory device are controlled using the set command data. For example, when the external control circuit causes the semiconductor memory device to execute a desired operation, command data instructing the desired operation is generated and output to the semiconductor memory device. In the semiconductor memory device, for example, command data input by the command processing circuit shown in FIG. 2 is processed. That is, the input command data is temporarily stored in the command register, and the stored data is transferred to the command error detection circuit. The command error detection circuit determines whether the input command data corresponds to any of a plurality of preset command data, and determines whether the input command data matches any of the set command data. , The command data is output as command data. Command decoder 6
4 decodes the input command data, generates a control signal for executing the operation specified by the command data as a result of the decoding, and outputs the control signal to the memory cell array and its peripheral circuit 200.

On the other hand, if the command error detection circuit determines that the input command data does not correspond to any of a plurality of preset command data, that is, if the input command data cannot be identified, the command data is being transferred. It is determined that an error has occurred, and an error signal S _ERR is output as shown in FIG. In this case, for example, the semiconductor memory device again waits for a command, waits for command data retransmitted from the external control circuit,
Upon receiving the next command data, it shifts to the operation state instructed thereby.

In the above description, 8-bit command data has been described as an example. However, the present invention is not limited to this, and it goes without saying that other plural-bit codes can be used as command data. Absent. Further, in the above description, the method of setting command data is considered by dividing the 8-bit command data into upper 4 bits and lower 4 bits. However, the present invention is not limited to this. It is also possible to consider a method of setting command data by dividing the data into lower 5 bits. Furthermore, in the above description, if there is no data change of at least 2 bits in the command data, the command data is set so as not to cause erroneous recognition of the command. However, based on the same concept, for example, 3 bits or more are set. If there is no bit change, the command data is set so as not to cause erroneous recognition of the command, or if there is no bit change of the fourth bit or more, the command data is set so as not to cause erroneous recognition of the command. It goes without saying that command data resistant to the influence of noise and the like can be obtained.

As described above, according to the present embodiment, command data is set in advance so that command data having a plurality of bits is not erroneously recognized by other command data when no bit change occurs in two or more bits. Then, the external control circuit generates command data according to a desired operation and transfers the command data to the semiconductor memory device. The command data input in the semiconductor memory device is temporarily stored in a command register and output to a command error detection circuit. The command error detection circuit determines the presence or absence of a command error based on whether the input data code corresponds to any of preset command data, and generates a predetermined control signal by the command decoder when there is no command error. Then, the data is output to the memory cell array and its peripheral circuits, and when a command error is detected, a command wait state is set. As a result, even if a bit change occurs due to the influence of noise or the like during the transfer of command data, there is no erroneous recognition of the command, the malfunction of the memory due to the error can be prevented, and the malfunction prevention function can be realized with a simple circuit.

[0039]

As described above, according to the semiconductor memory device of the present invention, erroneous recognition of command data can be avoided.
There is an advantage that malfunction of the memory and its peripheral circuits can be prevented, and the purpose of malfunction prevention can be achieved with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a command processing circuit.

FIG. 3 is an example of command data, showing an example of setting command data in which upper 4 bits and lower 4 bits are different.

FIG. 4 is another example of command data, showing an example of setting command data that is not erroneously recognized unless there is a data change of 2 bits or more in the upper 4 bits.

FIG. 5 is a diagram showing another example of command data, and showing an example of setting command data which is not erroneously recognized unless there is a change in data of two or more bits in the lower 4 bits.

FIG. 6 is another example of setting of command data, and is a diagram showing an example of setting of command data in which erroneous recognition does not occur unless there is a change in data of 2 bits or more in 8-bit command data.

FIG. 7 is a diagram illustrating a configuration example of a commonly used command processing circuit.

FIG. 8 is a diagram showing an example of conventional command data.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... I / O control circuit, 20 ... Operation logic control circuit, 30 ... Status register, 40 ... Address register, 50 ... Command register, 52 ... Command error detection circuit, 60 ... Control circuit, 62, 64 ... Command decoder, 70 ... Row address buffer, 80 ...
Row address decoder, 90 ... memory cell array, 10
0: high voltage generation circuit, 101, 102: oscillation circuit, 10
3, 104: charge pump, 105: voltage conversion circuit,
106, 107: boost control circuit, 110: R / B circuit,
120: column buffer, 130: column decoder, 1
40: column register, 150: sense amplifier.

Claims (16)

[Claims] 1. A semiconductor memory device which performs an operation specified by an externally input command data of M bits (M is an integer of 2 or more) in accordance with the command data. And a command detection circuit that detects whether the received command data is identifiable. If the received command data is identifiable as a result of the detection by the command detection circuit, an operation specified by the command data is performed. The M-bit command data is composed of two parts, upper L (L <M) bits and lower N (N = ML) bits,
A semiconductor memory device having p command data instructing different kinds of operations (p <2 ^M ) in total, all the upper L bits of each command data being different, and all the lower N bits of each command data being different . 2. The semiconductor memory device according to claim 1, wherein said control circuit has a command decoder for decoding the received command data and generating a control signal for instructing an operation in accordance with a result of the decoding. 3. The semiconductor memory device according to claim 1, further comprising a command buffer for holding said command data. 4. The semiconductor memory device according to claim 3, wherein said M-bit command data is transferred from said external control circuit to said command buffer in parallel. 5. A semiconductor memory device which performs an operation specified by an externally input command data of M bits (M is an integer of 2 or more), wherein the command data of M bits is provided. And a command detection circuit that detects whether the received command data is identifiable. If the received command data is identifiable as a result of the detection by the command detection circuit, an operation specified by the command data is performed. The M-bit command data includes upper L (2 ≦ L <
M) bits and lower N (N = ML) bits, and has p pieces of command data for instructing p types (p <2 ^M ) of different operations in total. A semiconductor memory device in which upper L-bit data is set so as not to coincide with other command data when at least 2-bit data does not change. 6. The semiconductor memory device according to claim 5, wherein said control circuit has a command decoder for decoding received command data and generating a control signal for operation instruction in accordance with a result of the decoding. 7. The semiconductor memory device according to claim 5, further comprising a command buffer for holding said command data. 8. The semiconductor memory device according to claim 7, wherein said M-bit command data is transferred from said external control circuit to said command buffer in parallel. 9. A semiconductor memory device which performs an operation specified by an externally input command data of M bits (M is an integer of 2 or more), wherein the command data of M bits is provided. And a command detection circuit that detects whether the received command data is identifiable. If the received command data is identifiable as a result of the detection by the command detection circuit, an operation specified by the command data is performed. The M-bit command data includes lower-order N (2 ≦ N <
M) bits and upper (L = M−N) bits, and has p command data for instructing p types (p <2 ^M ) of different operations in total. A semiconductor memory device in which N-bit data is set so as not to coincide with other command data when at least 2-bit data does not change. 10. The command circuit according to claim 9, wherein said control circuit has a command decoder for decoding received command data and generating a control signal for operation instruction in accordance with a result of the decoding.
The semiconductor memory device according to claim 1. 11. The semiconductor memory device according to claim 9, further comprising a command buffer for holding said command data. 12. The semiconductor memory device according to claim 11, wherein said M-bit command data is transferred from said external control circuit to said command buffer in parallel. 13. A semiconductor memory device which performs an operation specified by command data of M bits (M is an integer of 2 or more) input from the outside, wherein the command data of M bits is provided. And a command detection circuit that detects whether the received command data is identifiable. If the received command data is identifiable as a result of the detection by the command detection circuit, an operation specified by the command data is performed. The M-bit command data has a total of p types (p <
2 ^M ) p command data instructing different operations, and each command data is set so as not to coincide with other command data when at least 2 bits of data do not change. . 14. The control circuit according to claim 1, wherein said control circuit has a command decoder for decoding received command data and generating a control signal for operation instruction in accordance with a result of the decoding.
3. The semiconductor memory device according to 3. 15. The semiconductor memory device according to claim 13, further comprising a command buffer for holding said command data. 16. The semiconductor memory device according to claim 15, wherein said M-bit command data is transferred from said external control circuit to said command buffer in parallel.