JPH11194975A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten access time by completing the write of one long word only through writing operation. SOLUTION: Corresponding to a read/write signal and the signals of strobe and data size from a CPU 2, a read necessity discriminating circuit 12 discriminates whether a write size is 8 bits (1 byte), 16 bits (1 word) or 32 bits (1 long word). In the case of write for 8 bits (1 byte) or 16 bits (1 word) as a result of discrimination, the read necessity discriminating circuit 12 outputs a control signal so as to perform operation conventionally in the order of a read control circuit 11 and a write control circuit 10. In the case of write for 32 bits (1 long word), the control signal is outputted so as not to operate the read control circuit 11 but to immediately operate the write control circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system capable of detecting and correcting an error by adding a plurality of redundant bits to valid data.

[0002]

2. Description of the Related Art In a memory system connected to a CPU, an ECC (Electro-Communication (ECC) system is used to ensure the reliability of data.
and an error detection and correction circuit (hereinafter referred to as “error correcting code”) using an error correcting code (error correcting code).
The error detection and correction of data are performed by mounting an error correction circuit.

FIG. 5 is a block diagram showing an example of a conventional memory system. It is assumed that the memory 1 of the memory system shown in FIG. 5 includes 32-bit data and 8-bit correction codes, and the data and correction codes have already been written by the error correction circuit 32. Hereinafter, an operation example of the memory system of FIG. 5 will be described with reference to the flowchart of FIG.

When the CPU 2 having a data width of 32 bits performs a partial write for writing data of 8 bits (1 byte) to the memory 1, the CPU 2 outputs a read / write signal, a strobe, data, and a signal of a data size. The read control circuit 11 receives a read / write signal and strobe from the CPU 2 and reads a read signal (OE-
N) is output, and 32-bit data Dr including 1-byte data to be written is read from the memory 1. At this time,
The 8-bit correction code ECC added to the 32 bits is also read (step S11). The 40-bit data Dr and ECC read from the memory 1 pass through the bus control circuit 4a, are latched by the latch circuit 5 by the latch signal output from the read control circuit 11, and are detected by the error detection and correction circuit 9 for data error detection. And correction (step S12). The partial write control circuit 6 is a CPU 2
A select signal for selecting the data Dp output from the CPU 2 or the 32-bit data Dr 'read from the memory 1 and passed through the error detection and correction circuit 9 according to the data size signal output from the CPU 2 is output.

The selectors 7a to 7d operate in response to a select signal from the partial write
Either the data Dp output from the CPU 2 and passed through the bus control circuit 4b as the write data Dw to the CPU 2 or the 32-bit data Dr 'read from the memory 1 and passed through the error detection and correction circuit 9 is selected every 8 bits. (Step S13). The correction code generation circuit 8 includes selectors 7a to 7a.
An 8-bit correction code ECC is generated from the 32-bit write data Dw (Dw1 to Dw4) selected by the selector 7d (step S14). The write control circuit 10 receives a read / write signal and strobe from the CPU 2, and outputs a control signal of the bus control circuit 4a and a write signal (WE-N) to the memory 1. The 32-bit write data Dw selected by the selectors 7a to 7d and the 8-bit data ECC generated by the correction code generation circuit 8 are written to the memory 1 by a control signal of the write control circuit 10 (Step S15).

The CPU 2 has 16 bits (1 word),
When writing 32-bit (1 long word) data to the memory 1, the same operation as when writing 8-bit (1 byte) data is performed.

[0007]

As described above, in the conventional memory system, when the CPU writes data to the memory, the CPU first reads out 32-bit data and an 8-bit correction code from the memory, and reads the 32-bit data. The CPU rewrites the data that the CPU is trying to write, and newly generates an 8-bit correction code to write the data to the memory. However, even when the CPU writes 32-bit data that does not become a partial write, since the 32-bit data is read from the memory, there is a problem that only the access time becomes longer.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory system capable of shortening an access time when a CPU writes data to a memory. .

[0009]

SUMMARY OF THE INVENTION The present invention relates to a memory system for detecting and correcting an error by adding a plurality of redundant bits to valid data. And an error correction circuit having a correction function and capable of performing a partial write, a read control circuit for performing the partial write, a write control circuit for writing to a memory, and the read control circuit for writing data to the memory And a reading necessity judging circuit for judging whether or not to operate. Further, the object of the present invention is to provide a CPU which has a data width of 16 bits or more, enables a cache during normal operation, and uses write-back having a fixed data width, and an error detecting and correcting the error. This is achieved by including a correction circuit, and an error detection / correction selection circuit that selects whether data corrected by the error correction circuit is valid or data not passing through the error correction circuit is valid.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In one embodiment of the present invention, a CPU
When writing 32-bit data (data having the same size as the memory access unit) to the memory, the access time is shortened by eliminating the operation of reading the 32-bit data from the memory. In another embodiment of the present invention, in the initial operation before the cache is validated, when writing 8-bit, 16-bit, or 32-bit data to the memory, the 32-bit data is once transferred from the memory. Normal operation in which writing is performed without reading an 8-bit correction code and when data is read, error detection and data correction are not performed, the cache is enabled, and data is used in a 32-bit fixed write-back. At times, when the CPU writes data to the memory, the access time is shortened by controlling the operation of reading out 32-bit data and the 8-bit correction code from the memory, thereby shortening the access time and further improving the reliability of the circuit. I try to improve. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The functions of the components denoted by the same reference numerals as those in FIG.

In the memory system shown in FIG. 1, a reading necessity judging circuit 12 is connected between a CPU 2 and a writing control circuit 10 and a reading control circuit 11, and the writing control circuit 1
The read necessity determination circuit 12 determines whether or not to operate the read control circuit 10 before operating 0, that is, whether or not it is necessary to read data from the memory 2 at the time of data write processing to the memory 2. When necessary, as in the case of partial writing, the operation is performed in the same manner as in the prior art, and when unnecessary, the data from the CPU 2 is written into the memory 2 without performing the reading operation. Less than,
An operation example at the time of writing data will be described by taking as an example a case where a memory access unit (data width) is 32 bits.

In FIG. 1, a reading necessity determination circuit 12
Determines whether the write size is 8 bits (1 byte), 16 bits (1 word), or 32 bits (1 long word) based on a read / write signal, strobe, and data size signal from the CPU 2. As a result of the determination, if the writing is of 8 bits (1 byte) and 16 bits (1 word), the reading necessity determination circuit 12 is controlled to perform the operation of the conventional read control circuit 11 and write control circuit 10 in the conventional order. Output a signal. 32 bits (1 long word)
In the case of writing, the control signal is output so that the read control circuit 11 does not operate and the write control circuit 10 operates immediately.

FIG. 2 is a diagram showing write timing in the memory system of the present invention. As shown in FIG. 2A, at the time of writing of 8 bits or 16 bits, a read signal (OE-N) is output from the read control circuit 11 to the memory 1 as in the conventional case, and then the write is performed. The control circuit 10 outputs a write signal (WE-N). That is, the data Dr and the correction code ECC
Is read out and passed through the error detection and correction circuit 9
r ′ or the data Dp from the CPU 2 is selected every 8 bits, and when the selected write data Dw and its correction code ECC are output to the bus control circuit 4a, the write control circuit 10 outputs the write signal (WE-N ) Is output. On the other hand, as shown in FIG. 2B, when writing 32 bits (1 long word), the read control circuit 11 does not output the read signal (OE-N) to the memory 1 and the write control circuit 10 From the write signal (WE-
N) is output immediately.

Therefore, the CPU 2 and the write control circuit 1
0, by connecting the read necessity determination circuit 12 with the read control circuit 11, when writing 32-bit (1 long word) data, only the write operation is required, so that the access time can be shortened. .

FIG. 3 is a block diagram showing another embodiment of the present invention. The functions of the components denoted by the same reference numerals as those in FIG. The memory 1 is composed of 32-bit data and 8-bit correction codes, and the data and correction codes have already been written by the error correction circuit 31 without errors.

The memory system shown in FIG.
1, a selector 14 is connected between the error detection / correction circuit 9 and the bus control circuit 4b, and an error detection / correction selection circuit 13 is connected between the selector 14 and the CPU 2 to enable the cache before validating. During the initial operation, and during the normal operation in which the cache is enabled and the data width is fixed and the write-back is performed, the CPU is executed without performing the read operation.
2 is written in the memory 1. Hereinafter, description will be given along the flowchart of FIG.

When the CPU 2 writes the 8-bit data Dp to the memory 1 during a period before the cache (not shown) is validated, the 32-bit data Dr and the 8-bit correction are once read from the memory 1 as shown in the prior art. Code ECC
Is written without performing the operation of reading (step S
1). Therefore, the 24-bit data and the 8-bit correction code that are not written into the memory 1 remain the initial data. Further, in order to select the 32-bit data Dr and Dr 'input to the selector 14, the output signal of the error detection and correction selection circuit 13 is set by the address, data and strobe of the CPU 2.

When the written 8-bit data Dw (= Dp) is read out, the 24-bit data and the correction code remain as initial data, and the error detection and correction of the error Data Dr and 8
Since the correction is performed based on the bit correction code ECC, the error detection and correction circuit 9 may perform error detection and correction. In order to allow the selector 14 to output the data Dr that does not pass through the error detection and correction circuit 9 to the bus control circuit 4b,
PU2 sets the error detection and correction selection circuit 13 (step S2). In this state, since the error detection and correction are not performed, the written 8-bit data Dw can be read (step S).
3). If an error occurs in the read 8-bit data Dw, an illegal instruction or the like is generated, so that the CPU 2 performs exception processing and stops. When the CPU 2 writes 16-bit (1 word) and 32-bit (1 long word) data to the memory 1, the same operation as the case of writing 8-bit (1 byte) data is performed.

Next, the CPU 2 validates the cache and
If the setting is made to use the fixed-bit write-back (step S4), the CPU 2 sets the selector 14 to output the 32-bit data Dr 'that has passed through the error detection and correction circuit 9 to the bus control circuit 4b. The error detection / correction selection circuit 13 is set (step S5). In addition, since the correction code of the memory 1 is not the correction code of the 32-bit data written in the memory 1 in the above-described writing to the memory 1, the CPU 2 writes the correction code ECC of 8 bits into the memory 1 so that the 32-bit correction code ECC is written in the memory 1. The memory 1 is initialized with the data (step S6). After initializing the memory 1, the CPU 2 reads and writes data at a fixed 32 bits (step S7). Therefore, when the CPU 2 writes data to the memory 1, it is not necessary to read out 32-bit data and an 8-bit correction code from the memory 1 once.
Since only a write operation is required, the access time can be shortened, and the circuit is simplified, so that the reliability of the circuit is improved.

[0021]

According to the memory system of the first aspect, the CP
By connecting a read necessity determination circuit between U and the write control circuit and the read control circuit, when writing 32-bit (1 long word) data, only the write operation is required, thereby shortening the access time. Can be. According to the memory system of the present invention, when the CPU writes data to the memory, the operation of reading out 32-bit data and the 8-bit correction code from the memory is eliminated, and only the write operation is required at the time of writing. The time can be shortened, and the reliability of the circuit is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a memory system of the present invention.

FIG. 2 is a timing chart showing write timing in one embodiment of the memory system of the present invention.

FIG. 3 is a block diagram showing another embodiment of the memory system of the present invention.

FIG. 4 is a flowchart illustrating an operation example according to another embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional memory system.

FIG. 6 is a flowchart showing an operation example of a conventional memory system.

[Explanation of symbols]

 Reference Signs List 1 memory 2 CPU 31, 32 error correction circuit 4a, 4b bus control circuit 5 latch circuit 6 partial write control circuit 7a to 7d selector 8 correction code generation circuit 9 error detection and correction circuit 10 write control circuit 11 read control circuit 12 read required Rejection determination circuit 13 Error detection and correction selection circuit 14 Selector

Claims (2)

[Claims] An error correction circuit having a function of detecting and correcting an error by adding a plurality of redundant bits to valid data and having a function of detecting and correcting the error and capable of performing a partial write. A read control circuit for performing a partial write, a write control circuit for writing to a memory, and a read control for writing without operating the read control circuit when the write data has the same size as the data width of the memory. A memory system comprising a rejection determination circuit. 2. A memory system for detecting and correcting an error by adding a plurality of redundant bits to valid data, having a data width of 16 bits or more, enabling a cache during normal operation, and A CPU that uses fixed-width write-back, an error correction circuit that detects and corrects the error, a cache enabled, and
When performing write-back with a fixed data width, the data corrected by the error correction circuit is validated, and during the initial operation before the cache is validated, the error detection / correction selection that validates data that does not pass through the error correction circuit is performed. And a circuit.