JPH06250937A - Method for memory control, memory control circuit with ecc function and information processor - Google Patents

Abstract

PURPOSE: To suppress the increase of the number of times of memory access at the time of adding an ECC code to each data with specific length and operating an ECC processing, and to prevent the executing speed of a program from being sharply deteriorated even at the time of executing the ECC processing. CONSTITUTION: At the time of adding an ECC code to each data with specific bit length and writing the data in a memory element 20, when the length of writing data from a CPU 10 is less than the specific bit length, data previously read from the memory element 20 are held in a mean 42 different from the memory element 20, and data with the specific bit length are generated based on the held data and the writing data from the CPU 10. Thus, the ECC processing can be attained even when the reading from the memory is not necessarily operated before the writing in the memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller for a system having an ECC (Error Check and Correction) function.

[0002]

2. Description of the Related Art In an information processing apparatus having an ECC processing function, an ECC code is added to each piece of data of a specific length from a CPU and stored in a system memory. For example,
In the Hamming code check method most commonly used at present, a 7-bit length ECC code is added to 32-bit length data. An 8-bit length ECC code is added to 64-bit length data. Therefore, an E equipped with a 32-bit CPU
For personal computers with CC function, ECC
From the viewpoint of saving the storage capacity for the code, an 8-bit length ECC code may be added to each 64-bit data regardless of the bit length of the information from the CPU.

In such a case, a method called read-modify-write is usually used when writing to the memory. In read-modify-write, memory information is read from memory locations consecutive to the write address before writing to the memory. Next, 64-bit write information is generated based on the read information and the write information from the CPU, and an 8-bit ECC code is added to the generated 64-bit information and written in the memory. In a 32-bit type CPU, the maximum data width of one-time write information from the CPU is 32 bits, which is less than 64 bits, so that read-modify-write is always performed when writing to the memory.

The prior art will now be described in more detail with reference to the drawings. FIG. 3 shows an example of the configuration of a conventional information processing system. In the figure, the information processing system 1 has a C
The PU 10 is provided. The CPU 10 is a 32-bit type processor, which outputs a 32-bit address signal on the address line 12 and outputs 8-bit, 16-bit, 24-bit, or 32-bit information on the data line 14. The address line 12 of the CPU 10 is input to the memory controller 16, and the output of the memory controller 16 is connected to the memory element 20. The memory element 20 is composed of eight memory blocks 20-0 to 20-7.

Based on the address signal output from the CPU 10, the memory controller 16 controls the row address signal, the column address signal, and the RAS (row address signal).
Strobe) signal and CAS (column address
Strobe signal is output to the memory element 20.
The row address and the column address are stored in the memory device 2
0 is commonly given to each memory block. The row address and the column address specify one storage area 100 in each of the memory blocks.
Storage area 100 is 8-bit (1 byte) data 100
A and 1-bit ECC code 100B. RA
The S signal and the CAS signal consist of eight memory blocks 20-
Used to specify one of 0 to 20-7.

When ECC processing is performed on data of each 64-bit length, the data of 64-bit length is accessed to the memory element 20 at once. In this case, 8
The memory blocks 20-0 to 20-7 are simultaneously accessed, and the memory device 20 as a whole has 6
4-bit length (8-bit length x 8) data bits and 8
One storage area for an ECC code having a bit length (1 bit length × 8 pieces) is designated.

The data on data line 14 is provided to ECC code generator 24 via mixer 22.
The data output from the CPU 10 onto the data line 14 is either 8 bits, 16 bits, 24 bits or 32 bits, but the data supplied from the mixer 22 to the ECC code generator 24 is always 64 bits. E
CC generator 24 has 8 bits for 64-bit data
A bit ECC code is generated, and an 8-bit ECC code is given to the memory element 20 together with 64-bit data.

Of the 64-bit data read from the memory device 20 and the 8-bit ECC code, 72-bit information including the ECC code is supplied to the error bit detection circuit 32. Of the 64-bit data read from the memory element 20 and the 8-bit ECC code, 64-bit data not including the ECC code is supplied to the error / bit correction circuit 34. The error bit correction circuit 34 includes an error bit detection circuit 32.
To correct the error bit in the 64-bit data. Error by the error bit correction circuit 34
The 64-bit data with the corrected bits is the mixer 22.
Given to. The mixer 22 synthesizes the 64-bit data in which the error bits have been corrected and the data from the CPU 10 to generate 64-bit data. Further, the 64-bit data whose error bits have been corrected by the error bit correction circuit 34 is also given to the read buffer 28. The CPU 10 reads the data in the read buffer 28 twice in 32-bit units.

Read modify write performed in such a conventional structure will be described. The case where the data "A"("A" is 8-bit data) at address 0 is rewritten to the data "B"("B" is 8-bit data) will be taken up. As shown in FIG. 2, all the data of "A" is stored in each 8-bit storage area in the storage area of 64 bits (8 bits × 8 pieces) as a whole from address 0 to address 7 before data rewriting. Is stored, and "A" in address 0 is changed to "
Although it is rewritten to B ″, data rewriting is not performed for the seven storage areas of address 1 to address 7.

The CPU 10 outputs an address 0 signal (32 bits) on the address line 12 and outputs 8-bit data ("B") on the data line 14. This 8
Prior to writing bit data (“B”) to the memory element 20, 64-bit data (“AAAAAAAA”) is read from the memory element 20. In order to read 64-bit data ("AAAAAAAA"), the memory controller 16 outputs a common row address and column address to the eight memory blocks, and outputs the common row address and column address from the eight memory blocks. Read data at the same time. This 64-bit data ("AAAAAA"
AA ″) is data stored in the 64-bit storage area from address 0 to address 7 of the memory element 20.

From the memory device 20, 8-bit ECC code is read out in addition to 64-bit data ("AAAAAAAA"). 64-bit data ("AAAAAA"
The AA ") and the 8-bit ECC code are fetched by the error bit detection circuit 32. The error bit detection circuit 32 and the error bit correction circuit 34 detect the error of the 64-bit data (" AAAAAAAA "). Bit correction is performed.

The error-bit-corrected 64-bit data ("AAAAAAAA") is supplied to the mixer 22, which then reads the 64-bit data ("AAAAAAAA" from the memory element 20 in this manner.
A ") and 8-bit data (" B ") from the CPU 10 are combined to newly add 64-bit data (" BAAAA ").
AA ") is output. ECC code generator 24
Is the 64-bit data ("B
An ECC code is generated for AAAAAA ").
The 64-bit data ("BAAAA" generated in this way
AAA ″) and the ECC code are written in the memory device 20.

In such an example of the prior art, in order to write 8-bit data "B" to address 0 of the memory element 20, 64-bit data ("AAAAAAAA" in address 0 to address 7 of the memory element 20 is written. After reading "", 64-bit data to be written ("BAAA
(AAAAA ") and write the generated 64-bit data (" BAAAAAAA ") to the memory element 20. That is, the read-modify-write operation is performed every time data is written to the memory. Since the access operation to the memory is required twice, the write operation to the memory is slowed down, and thus the execution speed of the program on the personal computer is prevented from being increased.

In Japanese Patent Laid-Open No. 4-219700, an address holding data in which an error has been detected and corrected data are stored in an address storage circuit and a correction data storage circuit, respectively, and then the address is accessed. There is shown a semiconductor memory device in which when the address is detected by the address comparison circuit, the data is read from the modified data storage circuit instead of being read from the memory location corresponding to the address. However, this application does not suggest the present invention.

[0015]

An object of the present invention is to suppress an increase in the number of memory accesses associated with ECC processing,
It is an object of the present invention to provide a memory control method, a memory control circuit with an ECC function, and an information processing device that do not cause a large reduction in the execution speed of a program even if a process is executed.

[0016]

In order to achieve the above object, a memory control method according to the present invention provides a write information from a CPU when an ECC code is added to each piece of information of a specific bit length and the information is written in a memory element. Is less than the specific bit length, the information previously read from the memory element is held in a means different from the memory element, and the held information and the write information from the CPU are held. The information of the specific bit length is generated based on the above, and the ECC process can be performed without necessarily reading from the memory before writing to the memory.

Further, the memory control circuit with an ECC function according to the present invention comprises: (a) a storage area for each specific bit length including a storage area of a memory element corresponding to the CPU address based on the CPU address from the CPU. Address generating means for outputting address information for specifying
ECC code generating means for generating an ECC code for the information for each specific bit length, and (c) read information holding means for holding the information of the specific bit length read from the memory element. And (d) ECC means for correcting the information in the read information holding means using the ECC code, and (e) CPU address holding for holding the CPU address used when reading or writing information. Means, (f) address comparing means for comparing the CPU address generated by the CPU when writing information to the memory element with the CPU address held in the CPU address holding means, and (g) the address comparison. According to the comparison result of the means, the specific bit is based on both the information in the read information holding means and the information from the CPU. Generates length information so as to have a, and write information generating means for providing to the ECC means and to allow the ECC processing not necessarily performed reading from the memory before writing to the memory.

[0018]

Embodiments of the present invention will now be described with reference to the drawings. The same or similar parts as those of the conventional example will be designated by the same reference numerals and the description thereof will be omitted or simplified. FIG. 1 shows an embodiment of an information processing system according to the present invention. In the figure, the address signal output from the CPU 10 of the information processing system 1 is applied to the address latch 42 and the address comparator 44 in addition to the memory controller 46. Address latch 42 holds the value of the address signal on address line 12. The address comparator 44 compares the address value held in the address latch 42 with the value of the address signal newly appearing on the address line 12.

The memory controller 46 performs an access operation to the memory element 20 in response to the comparison result of the address comparator 44. The data read from the memory element 20 is held in the read / write buffer 26, and after the data held in the read / write buffer 26 is error-corrected, it is combined with the data from the CPU 10 in the mixer 22 to obtain the ECC. It is adapted to be written in the memory element 20 via the code generator 24.

In such an embodiment, as shown in FIG. 2, a case where the data "A" at address 0 is rewritten to the data "B" will be described. First, CP
The U10 outputs an address 0 signal (32 bits) on the address line 12 and outputs 8-bit data ("B") on the data line 14. The address latch 42 holds the address of the memory element 20 at the time of the previous reading. Here, it is assumed that the address at the time of the previous reading is any one of the addresses 0 to 7. In this case, the read / write buffer 26 has previously read data, that is, 64-bit data ("
AAAAAAAA ″) is held.

The address comparator 44 is the CPU 1
The address 0 newly output (address 0 in this case) is compared with the address value held in the address latch 42. When the address value newly output by the CPU 10 is the address 0, the address value held in the address latch 42 is changed from the address 0 to the address 7
If it is any of the above, a signal indicating that is given from the address comparator 44 to the memory controller 46, and the memory controller 46 causes the memory element 20 to operate.
The read operation for read modify write is not performed. As described above, when the address value held in the address latch 42 is any one of the addresses 0 to 7, the read / write buffer 26 has 64-bit data as the previously read data. The data ("AAAAAAAA") is held.

The mixer 22 receives the 64-bit data ("AAAAA" supplied from the read / write buffer 26).
AAAA ") and 8-bit data (""from the CPU 10
B ") and newly combine with 64-bit data (" BAA
The ECC code generator 24 generates an ECC code for the 64-bit data ("BAAAAAAA") generated by the mixer 22. The 64-bit data (" BAAAAAAA ″) and the ECC code are written to the memory element 20.

When the address value newly output by the CPU 10 is the address 0 and the address value held in the address latch 42 is not one of the addresses 0 to 7, a signal indicating that fact. Is the address
The data is supplied from the comparator 44 to the memory controller 46, and the memory controller 46 performs a read operation for read-modify-write on the memory element 20.

According to this embodiment, the means for holding the address and the data of the immediately preceding memory cycle is provided, so that the ECC processing is performed on the data of each specific bit length. The number of memory readings for read-modify-write can be reduced. In some cases, the data read in the last memory cycle may not be available. However, in executing a program, it is often the case that successive addresses of the memory element 20 are sequentially accessed. When accessing consecutive addresses in order, the data of the immediately preceding memory cycle is often available, and read modify
The number of read operations for writing can be sufficiently reduced.

In the above embodiment, an 8-bit ECC code is added to each 64-bit data, but the present invention may be applied to data having a length other than 64 bits. Accordingly, the length of the ECC code may be other than 8 bits. Further, the CPU does not have to be a 32-bit type and may be a RISC type or a CISC type. The configuration of the memory element is not limited to the above configuration,
Interleaved access method or non-interleaved
It does not matter whether it is an access method or the like.

[0026]

As described above, according to the present invention, it is possible to suppress an increase in the number of memory accesses associated with ECC processing,
It is possible to provide a memory control method, a memory control circuit with an ECC function, and an information processing device that do not cause a large reduction in the execution speed of a program even if a process is executed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a data processing system having an ECC processing function according to the present invention.

FIG. 2 is a block diagram showing an example of a configuration of data before and after writing to a memory.

FIG. 3 is a block diagram showing a configuration of an example of a conventional data processing system having an ECC processing function.

[Explanation of symbols]

 1 Information Processing System 10 CPU 16 Memory Controller 20 Memory Element 22 Mixer 24 ECC Code Generator 26 Read / Write Buffer 28 Read Buffer 32 Error Bit Detection Circuit 34 Error Bit Correction Circuit 42 Address Latch 44 Address Comparator 46 memory controller

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Innovator Nobuto Fujita 800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture In the Yasu Business Office, IBM Japan, Ltd. (72) Satoshi Yamazaki 1623 Shimotsuruma, Yamato-shi, Kanagawa Prefecture Address 14 Japan AIBM Co., Ltd. Yamato Works (72) Inventor Mitsuhiro Goda 1623 Shimotsuruma, Yamato City, Kanagawa Prefecture 14 Japan AIBM Co., Ltd. Yamato Works

Claims (3)

[Claims] 1. When an ECC code is added to each piece of information of a specific bit length and written in a memory element, if the write information from the CPU is less than the specific bit length, it is read from the memory element before. Information is held in a means different from the memory element, and the information of the specific bit length is generated based on the held information and the write information from the CPU. , Memory control method. 2. An EC interposed between a CPU and a memory element
In the memory control circuit with C function, (a) for outputting address information for specifying a storage area for each specific bit length including a storage area of the memory element corresponding to the CPU address, based on the CPU address from the CPU Address generating means, (b) ECC code generating means for generating an ECC code for the information for each specific bit length, and (c) the specific bit length information read from the memory device. Read information holding means for holding the information, and (d) the information in the read information holding means
ECC means for correction using CC code,
(E) CP used when reading or writing information
CPU address holding means for holding the U address, and (f) an address for comparing the CPU address generated by the CPU at the time of writing information to the memory element with the CPU address held in the CPU address holding means. And (g) the information in the read information holding means and C in accordance with the comparison result of the address comparing means.
A memory control circuit with an ECC function, comprising: write information generating means for generating the information of the specific bit length based on both of the information from the PU and giving it to the ECC means. 3. An information processing apparatus comprising a CPU, a memory element, and a memory control circuit with an ECC function interposed between the CPU and the memory element, wherein the memory control circuit comprises: Address generation means for outputting address information for specifying a storage area for each specific bit length including the storage area of the memory element corresponding to the CPU address,
ECC code generating means for generating an ECC code for the information for each specific bit length, and (c) read information holding means for holding the information of the specific bit length read from the memory element. And (d) ECC means for correcting the information in the read information holding means using the ECC code, and (e) CPU address holding for holding the CPU address used when reading or writing information. Means, (f) address comparing means for comparing the CPU address generated by the CPU when writing information to the memory element with the CPU address held in the CPU address holding means, and (g) the address comparison. According to the comparison result of the means, the specific bit is based on both the information in the read information holding means and the information from the CPU. It generates the length information having a write information generating means for providing to the ECC unit,
Information processing equipment.