JP2565590B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention detects and corrects an error in input data and adds an error detection and correction code to output data in inputting and outputting data. The present invention relates to a data processing device incorporating an error correction detection circuit.

[Conventional technology]

2. Description of the Related Art Conventionally, a semiconductor memory has been used as a main memory in a data processing device, and in recent years, a DRAM (dynamic random access memory) whose capacity has been increasing is often used for the main memory. However, DRAM may cause a soft error, and in order to ensure data reliability in data transfer between the storage device and the arithmetic unit, SEC-DEC
An error detection / correction circuit using a code or the like is used.

An example of a conventional data processing apparatus including this type of error detection and correction circuit will be described with reference to FIGS. 6 and 7.

In FIG. 6, the data processor is an external data bus.
66, an input data latch 61 and an output data latch 62 for temporarily storing data, a register 63 for storing a plurality of data, an error detection / correction circuit 65, an output of the input data latch 61 and an output of the register 63 are input. A selector 64 for outputting one of them to the error detection / correction circuit 65, a write bus 67 for writing data in the output data latch 62 and the register 63, and a control path 68 for controlling the above circuits are included.

As shown in FIG. 7, the control circuit 68 includes an instruction decoder 73 that decodes an instruction code, a write register address latch 72 that temporarily holds an address (register number) to the write register in the register 63, and a read register read operation. A read register address latch 71 for temporarily holding an address (register number) is included.

Next, the operation when the data processing device executes the data input command and the data output command will be described with reference to FIG. First, when executing a data input command,
In the first cycle, the data input from the external data bus 66 is temporarily stored in the input data latch 61. In the second cycle, the output of the input data latch 61 is selected by the selector 64, the error detection and correction circuit 65 performs error detection and correction on this data, and the corrected data is registered in the register 63 designated by the data input instruction. Store through write bus 67. The register number of the register 63 for storing the data is designated by the data input instruction and is held in the write register address latch 72.

Next, when executing the data output instruction, in the first cycle, the register number of the read register specified by this data output instruction is held in the read register address latch 71, and the data stored in the register 63 is stored. read out. This data is selected by the selector 64 and input to the error detection / correction circuit 65, and the error detection / correction circuit 65 generates / adds an error detection / correction code to the data. In the second cycle, the data to which the error detection and correction code is added is temporarily stored in the output data latch 62 via the write bus 67 and output to the external data bus 66.

As described above, in the data processing device incorporating the error detection / correction circuit 65, the data read from the storage device passes through the error detection / correction circuit 65 at the time of input, and is corrected when the data contains an error. When outputting data, the output data is stored in the storage device with an error detection and correction code added.

[Problems to be Solved by the Invention]

However, in the conventional configuration as described above, when the data input instruction is followed by the data output instruction, the error correction detection circuit 65 is used by these two instructions, so that as shown in FIG. Error correction detection circuit used
The data output instruction is executed after 65 becomes available in the next cycle. That is, data input is performed in the first cycle, error correction and register writing are performed in the second cycle, register reading and error detection / correction code generation / addition are performed in the third cycle, and the fourth cycle is performed.
The data is output in the cycle.

As described above, even if the data input command and the data output command are continuously given, there is a problem that the data output command has a waiting time and the processing becomes slow. If the register to be written by the data input instruction is the same as the register to be read by the data output instruction, the same data will be repeatedly passed twice through the error detection / correction circuit 65, and the error detection / correction circuit 65 is used. There was a problem that the processing speed was slow because it was wasted once.

An object of the present invention is to provide a data processing device capable of efficiently controlling an error detection / correction circuit and avoiding a wasteful cycle when a data output command follows a data output command.

[Means for solving the problem]

A data processing device according to claim (1) stores an input data latch for temporarily storing data input from an external data bus, an output data latch for temporarily storing data to be output to the external data bus, and a plurality of data. A register, a write bus that supplies data to be input to the register and the output data latch, and error detection and correction for the data read from the input data latch and an error detection and correction code for the data read from the register Controls the error detection and correction circuit that generates and adds the error detection and correction data and outputs the data to which the error detection and correction code is added to the write bus, the input data latch, the output data latch, the register, and the error detection and correction circuit. And a control circuit for controlling.

The control circuit has an instruction decoding function for decoding an instruction and a data input instruction for storing the data input from the external data bus in the register, followed by a data output instruction for outputting the data stored in the register to the external data bus. Command combination detection function to detect that, when the data output command follows the data input command,
In the first cycle, the data input from the external data bus is temporarily stored in the input data latch, the data is read from the register number included in the data output instruction of the register, and is sent to the error detection / correction circuit. The detection / correction code generation / addition is executed, the data to which the error detection / correction code is added is output to the write data bus, and the data output to the write data bus is temporarily stored in the output data latch. In the cycle, the data temporarily stored in the output data latch is output to the external data bus, the data is read from the input data latch and sent to the error detection / correction circuit, the error detection / correction is executed for this data, and the error detection / correction is performed. The data is output to the write data bus and the register data is output through the write data bus. And a control function of writing the specified register number input command.

The data processing device according to claim (2) is based on claim (1).
The control circuit is different from that of FIG.

The control circuit has an instruction decoding function for decoding an instruction and a data input instruction for storing the data input from the external data bus in the register, and a data output instruction for outputting the data stored in the register to the external data bus. The instruction combination detection function that detects that a match is detected, the match detection function that detects a match between the register number included in the data input instruction and the register number included in the data output instruction that follows the data input instruction, and after the data input instruction When the data output instruction continues and the register number of the register written by the data input instruction matches the register number read by the data output instruction, the data input from the external data bus is input to the input data latch in the first cycle. Temporarily store and read data from input data latch in the second cycle Send to the error detection and correction circuit, execute error detection and correction on this data, write the error-corrected data to the register through the write data bus, and temporarily store it in the output data latch. It has a control function of outputting the data temporarily stored in the latch to the external data bus.

The data processing device according to claim (3) is the data processing device according to claim (1).
The control circuit is different from that of FIG.

The control circuit has an instruction decoding function for decoding an instruction and a data input instruction for storing the data input from the external data bus in the register, followed by a data output instruction for outputting the data stored in the register to the external data bus. The instruction combination detection function that detects that a match is detected, the match detection function that detects a match between the register number included in the data input instruction and the register number included in the data output instruction that follows the data input instruction, and after the data input instruction When the data output instruction continues, and when the first register number of the register written by the data input instruction and the second register number read by the data output instruction match, the data is input from the external data bus in the first cycle. The data is temporarily stored in the input data latch, and the data of the input data latch is stored in the second cycle. Output temporarily stored in the data latches, and outputs the temporary storage data to the output data latch to the external data bus, reads out the data from the input data latch sends to the error detection and correction circuit, to perform error detection and correction to this data,
The error-corrected data is output to the write data bus, written to the register through the write data bus, temporarily stored in the output data latch only when an error occurs, and only when an error occurs in the third cycle. It has a control function of outputting the data temporarily stored in the output data latch to the external data bus.

[Action]

According to the configuration of claim (1), when the data input instruction is followed by the data output instruction, the data input instruction and the data output instruction are executed in parallel, and the data output instruction is executed in the first cycle. The error detection / correction code is generated / added according to the above, and the error detection / correction is performed by the data input instruction in the second cycle. As a result, it is possible to efficiently use the error detection and correction circuit and perform processing so that external data input / output is continuous.

According to the configuration of claim (2), when the data input instruction is followed by the data output instruction and the register number of the register written by the data input instruction and the register number of the register read by the data output instruction match, After performing error detection and correction on the data stored in the input data latch, store it in the register and store it in the output data latch and output it to the external data bus. Data is not read from and the error detection and correction code is not generated or added.

According to the configuration of claim (3), when the data input instruction is followed by the data output instruction and the register number of the register written by the data input instruction and the register number of the register read by the data output instruction match, The data stored in the input data latch is stored in the output data latch as it is, and the uncorrected data is output to the external data bus. At the same time, the data stored in the input data latch is subjected to error detection and correction, and the corrected data is corrected. Is stored in the register and stored in the output data latch only when the correctable signal is generated, and the corrected data is output to the external data bus.Therefore, there is an error in the data output processing by the data output instruction. No detection / correction code is generated / added. If the data input by the data input command has no error, the corrected data is not output.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

As shown in FIG. 1, this data processing device includes an external data bus 16, an input data latch 11 for temporarily storing data input from the external data bus 16, and an external data bus 16.
Output data latch 12 for temporarily storing the data to be output to
And a register 13 for storing a plurality of data, and a selector 14 having a first input terminal connected to the output terminal of the input data latch 11 and a second input terminal connected to the output terminal of the register 13.
, A write bus 17 for supplying data to be input to the register 13 and the output data latch 12, and a selector 14 having an input terminal.
The error detection and correction of the input data connected to the output terminal of the device and the generation and addition of the error detection and correction code, and the error detection and correction data and the data with the error detection and correction code are output to the write bus 17 Circuit 15 and
A control circuit 18 for controlling each of the above circuits is included.

Specifically, as shown in FIG. 2, the control circuit 18 temporarily holds an instruction decoder 26 that decodes an instruction code including a control signal and a register number, and a register number when writing data to the register 13. A write register address latch 22, a read register address latch 21 that temporarily holds a register number when reading data from the register 13, a control signal latch 24 that temporarily stores a control signal, and a control signal obtained by decoding an instruction. An instruction combination detection circuit (corresponding to the instruction combination detection function in the claims) 25 having an input, a first input terminal connected to the output terminal of the read register address latch 21, and a second input terminal connected to the read register Address latch
A selector 23 connected to the input terminal of 21 to select a read address.

Next, the operation when this data processing device executes a data input / output instruction will be described with reference to FIG.
First, register the data input from the external data bus 16.
When the data input instruction to be stored in 13 is executed, in the first cycle, the data input from the external data bus 16 is temporarily stored in the input data latch 11. In the second cycle, the output of the input data latch 11 is selected by the selector 14 and this data is sent to the error detection / correction circuit 15. The error detection / correction circuit 15 performs error detection / correction on the input data and outputs the error-detected / corrected data to the write bus 17. The data on the write bus 17 is stored in the register 13 at the address (register number) designated by the data input instruction. The address of the register 13 designated by the data input instruction is sent from the instruction decoder 26 to the write register address latch 22 and held in the write register address latch 22.

Next, when executing a data output instruction for outputting the data stored in the register 13 to the external data bus 16,
In the first cycle, the address of the read register designated by this data output instruction is held in the read register address latch 21, and the selector 23 selects the address held in the read register address latch 21. The data stored in the register 13 designated by this address is read out and sent to the error detection / correction circuit 15. The error detection / correction circuit 15 generates / adds an error detection / correction code to the input data, outputs it to the write bus 17, and temporarily stores it in the output data latch 12. In the second cycle, the data stored in the output data latch 12 is output to the external data bus 16.

Next, the operation of the case where the data input instruction is followed by the data output instruction will be described with reference to FIG.
First, in the first cycle, after the execution of the data input instruction, the decode signal of the data input instruction is transferred to the control signal latch 24.
If the next instruction is decoded by the instruction decoder 26 during that time, the instruction combination detection circuit 25 compares the result of this decoding with the output of the control signal latch 24 to allow the data input instruction and the data output. Detects that the commands and are continuous. The detection result is the selector
The address sent to 23 and decoded is switched to the read register address of the data output instruction by this selector 23 and given to the register 13. As described above, in the first cycle, the data input operation by the data input instruction and the data read operation from the register 13 and the error detection and correction code generation operation by the data output instruction are simultaneously performed. That is, the data input from the external data bus 16 is temporarily stored in the input data latch 11, the data is read from the register number included in the data output instruction of the register 13 and sent to the error detection / correction circuit 15, and an error for this data is detected. The detection / correction code is generated / added, the data to which the error detection / correction code is added is output to the write data bus 17, and is temporarily stored in the output data latch 12. Next, the second
In the cycle of, the data stored in the output data latch 12 is output to the external data bus 16, the data is read from the input data latch 11 and sent to the error detection / correction circuit 15, and the error detection / correction for this data is executed, The error-corrected data is output to the write data bus 17 and written to the register number designated by the data input instruction of the register 13 through the write data bus 17.

As described above, as is apparent from FIG. 10, it is understood that the two instructions (data input instruction and data output instruction) are processed in parallel and no wasteful cycle occurs.

According to this embodiment, when the data input instruction is followed by the data output instruction, the data input instruction and the data output instruction are executed in parallel, and the error detection and correction code by the data output instruction is executed in the first cycle. Are generated and added, and error detection and correction are performed by the data input instruction in the second cycle. As a result, the error detection / correction circuit 15 can be efficiently used to process the input / output of external data continuously, and the data input process and the data output process can be continuously performed without waiting time. The processing speed can be increased.

A second embodiment of the present invention will be described with reference to FIGS. 1 and 3. In this data processor, the structure of the control circuit 18 'is different from that of the first embodiment, but the other structures are the same as those of the first embodiment.

Specifically, as shown in FIG. 3, the control circuit 18 'holds an instruction decoder 36 for decoding an instruction code including a control signal and a register number, and a register number for temporarily writing data in the register 13. A write register address latch 32, a read register address latch 31 that temporarily holds a register number when reading data from the register 13, a control signal latch 34 that temporarily stores a control signal, and a control that decodes an instruction. A command combination detection circuit (corresponding to the command combination detection function in the claims) 35 that receives a signal, and a match detection circuit (corresponding to the match detection function in the claims) that compares a read address and a write address. Including 33 and.

Next, in the second embodiment, in the case where the data input instruction is followed by the data output instruction and the register number of the register written by the data input instruction and the register number of the register read by the data output instruction match, The operation will be described with reference to FIG. First, in the first cycle, when the decode signal of the data input instruction is held in the control signal latch 34 after the execution of the data input instruction, if the next instruction is decoded by the instruction decoder 36 during that time, this decode Results and control signal latch 34
The instruction combination detection circuit 35 detects that the data input instruction and the data output instruction are continuous by comparing with the output of. At this time, the data input from the external data bus 16 is temporarily stored in the data latch 11 for input. Next, in the second cycle, when the data output instruction is in the instruction decoder 36 and the continuation of the instruction is detected, the write address of the data input instruction and the read address of the data output instruction are compared. As a result of this comparison, if the addresses match, the output of the match detection circuit 33 reads the data from the input data latch 11 and sends it to the error detection / correction circuit 15 by the selector 14 to execute the error detection / correction on this data. The error-corrected data is written to the register 13 through the write data bus 17 and temporarily stored in the output data latch 12. Next, the third
In the cycle, the data stored in the output data latch 12 is output to the external data bus 16.

According to this embodiment, a data input instruction is followed by a data output instruction, and a register written by the data input instruction
Register number of 13 and register read by data output instruction
When the register number of 13 matches, the data stored in the input data latch 11 is subjected to error detection and correction, and then stored in the register 13 and output data latch 12
Stored in the external data bus 16 and output to the external data bus 16, and data is not read from the register and the error detection and correction code is not generated or added during the data output processing by the data output instruction, that is, the same data as the input data. Is output, the data is not read from the wasteful register 13 and the error detection / correction code generation / addition processing is not performed, so that the data processing can be speeded up.

A third embodiment of the present invention will be described with reference to FIGS. 4 and 5. As shown in FIG. 4, this data processor temporarily stores an external data bus 46, an input data latch 41 for temporarily storing data input from the external data bus 46, and data to be output to the external data bus 46. An output data latch 42, a register 43 for storing a plurality of data,
The selector 44 having the first input terminal connected to the output terminal of the input data latch 41 and the second input terminal connected to the output terminal of the register 43, the write bus 47 for giving data to be input to the register 43, and the input terminal An error detection and correction circuit 45 connected to the output terminal of the selector 44 to output data to the write bus 47, and a second input terminal connected to the write bus 47 with the first input terminal
Output selector 49 with its input terminal connected to the input data latch 41 and its output terminal connected to the input terminal of the output data latch 42
And a control circuit 48 for controlling the above circuits.

Specifically, as shown in FIG. 5, the control circuit 48 decodes an instruction code including a control signal and a register number and inputs an error generation signal 57, and an instruction decoder 56 for writing data to the register 43. A write register address latch 52 that temporarily holds a register number, a read register address latch 51 that temporarily holds a register number when reading data from the register 43, and
A control signal latch 54 that temporarily stores a control signal, an instruction combination detection circuit (corresponding to the instruction combination detection function in the claims) 55 that receives a control signal obtained by decoding an instruction, a read address and a write address. And a coincidence detection circuit (corresponding to the coincidence detection function in claims) 53.

Next, in the third embodiment, the case where the data input instruction is followed by the data output instruction and the register number of the register written by the data input instruction and the register number of the register read by the data output instruction match The operation will be described with reference to FIG. First, in the first cycle, when the decode signal of the data input instruction is held in the control signal latch 54 after the start of execution of the data input instruction, and the next instruction is decoded by the instruction decoder 56 during that time, this decode The instruction combination detection circuit 55 detects that the data input instruction and the data output instruction are continuous by comparing the result of the above with the output of the control signal latch 54. When the data output instruction is in the instruction decoder 56 and the continuity of the instruction is detected, the write address of the data input instruction and the read address of the data output instruction are compared. At this time, the data input from the external data bus 46 is temporarily stored in the input data latch 41.

Next, in the second cycle, if the comparison result addresses match, the output of the match detection circuit 53 causes the output selector 49 to temporarily store the data of the input data latch 41 in the output data latch 42, and the output The uncorrected data temporarily stored in the data latch 42 is output to the external data bus 46, the data is read from the input data latch 41 and sent to the error detection / correction circuit 45 by the selector 44, and the error detection / correction for this data is executed. The error-corrected data is output to the write data bus 47 and written to the register 43 through the write data bus 47. At the same time, a correctable error generation signal 57 is generated due to an error in the data, which is input to the control circuit 48. Only when this is done, the output selector 49 temporarily stores it in the output data latch 42.

Next, in the third cycle, the correctable error occurrence signal
Only when 57 occurs, the data temporarily stored in the output data latch 42 is output to the external data bus 46. In other words, only when there is a correctable error in the data, the external data bus
Correctly corrected data will be output again in 46.

According to this embodiment, when the data output instruction is followed by the data output instruction, and the register number of the register to be written by the data input instruction and the register number of the register to be read by the data output instruction match, the input data latch 41
The data stored in the output data latch 42 is directly stored in the output data latch 42 and the uncorrected data is output to the external data bus 46. At the same time, the data stored in the input data latch 41 is subjected to error detection and correction to correct the data. Are stored in the register 43 and stored in the output data latch 42 only when the correctable error occurrence signal is generated.
The corrected data is output to 46, and the error detection and correction code is not generated / added during the data output processing by the data output instruction, that is, when the same data as the input data is output, it is wasteful. Since the error detection / correction code generation / addition processing is not performed, the data processing can be speeded up. Further, when there is no error in the data input by the data input command, the output process of the corrected data is eliminated, so that the data processing can be further speeded up.

〔The invention's effect〕

According to the data processing device of the first aspect, when the data input instruction is followed by the data output instruction, the data input instruction and the data output instruction are executed in parallel, and the data is output in the first cycle. The error detection and correction code is generated and added by the output instruction, and the error detection and correction is performed by the data input instruction in the second cycle. As a result, the error detection / correction circuit can be efficiently used to process the input / output of the external data continuously, and the data input process and the data output process can be continuously performed without waiting time. Can be speeded up.

According to the data processor of claim (2), when the data input instruction is followed by the data output instruction, and the register number of the register written by the data input instruction and the register number of the register read by the data output instruction match. In addition, after performing error detection and correction on the data stored in the input data latch, it is stored in the register and also stored in the output data latch and output to the external data bus. Does not read data from registers or generate / add error detection / correction codes, that is, when outputting the same data as input data, read data from wasteful registers and generate error detection / correction codes. -Since no additional processing is performed, the speed of data processing can be increased.

According to the data processor of claim (3), when the data input instruction is followed by the data output instruction, and the register number of the register written by the data input instruction and the register number of the register read by the data output instruction match. In addition, the data stored in the input data latch is stored in the output data latch as it is and the uncorrected data is output to the external data bus. At the same time, the data stored in the input data latch is subjected to error detection and correction to correct it. The corrected data is stored in the output data latch only when the correctable error occurrence signal is generated, and the corrected data is output to the external data bus. Does not generate or add error detection and correction code, that is, it outputs the same data as the input data. Case, does not perform the generation and addition processing of waste ECC code, the data processing can be accelerated. Further, when there is no error in the data input by the data input command, the output process of the corrected data is eliminated, so that the data processing can be further speeded up.

[Brief description of drawings]

1 is a schematic block diagram of a data processing apparatus showing a first embodiment of the present invention, FIG. 2 is a block diagram showing a control unit of FIG. 1, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a block diagram showing a control unit, FIG. 4 is a schematic block diagram of a data processing device showing a third embodiment of the present invention, FIG. 5 is a block diagram showing the control unit in FIG. 4, and FIG. FIG. 7 is a schematic block diagram of the data processing device, FIG. 7 is a block diagram showing the control unit of FIG. 6, FIG. 8 is a timing diagram showing the order of input / output, and FIG. Timing diagram showing continuous execution, FIG. 10 is a timing diagram showing continuous execution of input and output of the first embodiment of the present invention, and FIG. 11 is continuous execution of input and output of the second embodiment of the present invention. FIG. 12 is a timing diagram showing the continuous execution of input and output according to the third embodiment of the present invention. It is a timing diagram. 11 …… Input data latch, 12 …… Output data latch, 13
...... Register, 14 ...... Selector, 15 …… Error detection and correction circuit, 16 …… External data bus, 17 …… Write bus, 18…
… Control circuit, 21 …… Read register address latch,
22 …… Write register address latch, 23 …… Selector, 24 …… Control signal latch, 26 …… Instruction decoder

Claims (3)

(57) [Claims] 1. An input data latch for temporarily storing data input from an external data bus, an output data latch for temporarily storing data output to the external data bus, a register for storing a plurality of data, the register, and A write bus for supplying data to be input to the output data latch, and error detection and correction for the data read from the input data latch and generation of an error detection and correction code for the data read from the register・
An error detection / correction circuit for outputting the data to which the error detection / correction has been performed and the data to which the error detection / correction code has been added to the write bus, and control for controlling the input data latch, the output data latch, the register, and the error detection / correction circuit The control circuit includes an instruction decoding function for decoding an instruction, and a data input instruction for storing the data input from the external data bus in the register, the data stored in the register after the external input. An instruction combination detecting function for detecting that a data output instruction to be output to the data bus follows, and a data input from the external data bus in the first cycle when the data input instruction is followed by the data output instruction. Register number temporarily stored in the input data latch and included in the data output instruction of the register The data is read from the device and sent to the error detection / correction circuit, and the error detection / correction code is generated / added to this data, and the data to which the error detection / correction code is added is output to the write data bus. The data output to the bus is temporarily stored in the output data latch, the data temporarily stored in the output data latch is output to the external data bus in the second cycle, and the data is read from the input data latch. The data is sent to the error detection / correction circuit, the error detection / correction is performed on this data, the data subjected to the error detection / correction is output to the write data bus, and the register designated by the data input command of the register is passed through the write data bus. A data processing device having a control function for writing to a number. 2. An input data latch for temporarily storing data input from an external data bus, an output data latch for temporarily storing data to be output to the external data bus, a register for storing a plurality of data, the register, and A write bus for supplying data to be input to the output data latch, and error detection and correction for the data read from the input data latch and generation of an error detection and correction code for the data read from the register・
An error detection / correction circuit for outputting the data to which the error detection / correction has been performed and the data to which the error detection / correction code has been added to the write bus, and control for controlling the input data latch, the output data latch, the register, and the error detection / correction circuit The control circuit includes an instruction decoding function for decoding an instruction, and a data input instruction for storing the data input from the external data bus in the register, the data stored in the register after the external input. An instruction combination detection function that detects that a data output instruction to be output to the data bus continues, and a match between the register number included in the data input instruction and the register number included in the data output instruction that follows the data input instruction. A matching detection function, and a data input command followed by a data output command, and the data input When the register number of the register written by the instruction and the register number read by the data output instruction match, the data input from the external data bus is temporarily stored in the input data latch in the first cycle, In the cycle, data is read from the input data latch and sent to the error detection / correction code, error detection / correction is executed for this data, and the error-corrected data is written to the register through the write data bus, and A data processing device having a control function of temporarily storing in an output data latch and outputting the data temporarily stored in the output data latch to the external data bus in a third cycle. 3. An input data latch for temporarily storing data input from an external data bus, an output data latch for temporarily storing data output to the external data bus, a register for storing a plurality of data, the register, and A write bus for supplying data to be input to the output data latch, and error detection and correction for the data read from the input data latch and generation of an error detection and correction code for the data read from the register・
An error detection / correction circuit for outputting the data to which the error detection / correction has been performed and the data to which the error detection / correction code has been added to the write bus, and control for controlling the input data latch, the output data latch, the register, and the error detection / correction circuit The control circuit includes an instruction decoding function for decoding an instruction, and a data input instruction for storing the data input from the external data bus in the register, the data stored in the register after the external input. An instruction combination detection function that detects that a data output instruction to be output to the data bus continues, and a match between the register number included in the data input instruction and the register number included in the data output instruction that follows the data input instruction. A matching detection function, and a data input command followed by a data output command, and the data input When the first register number of the register written by the instruction and the second register number read by the data output instruction match, the data input from the external data bus is input to the input data latch in the first cycle. Temporarily store the data of the input data latch in the output data latch in the second cycle, output the data temporarily stored in the output data latch to the external data bus, and output the data from the input data latch. Is sent to the error detection / correction circuit, the error detection / correction is executed on this data, the data subjected to the error detection / correction is output to the write data bus, and the data is written to the register through the write data bus. Only when it occurs, temporarily store it in the output data latch and In Le, the data processing device and a control function of outputting the data stored temporarily in the output data latch only when an error occurs to the external data bus.