JPH10143448A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a rewrite operation from being turned to the waiting state of the access of an external input/output device by giving rewrite priority at all times in the case of read form a rewrite address at the time of reading memory. SOLUTION: In the case that an error is detected in data reading from a memory 101 and it is correctable, corrected data are outputted to the external input/output device as read data and stored in a rewritten data register 103 and an address which generates the error is simultaneously stored in a rewritten address register 106. To a memory access control circuit 105, a rewritten request signal for requesting the rewriting to the memory of the stored corrected data is outputted. A memory rewriting request/-memory writing request from the data input/output device and the rewriting request signal are inputted by the memory access control circuit 105, they are mediated and memory access from the input/output device is given with priority.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system using a RAM, and more particularly, to a memory system which reads data from a RAM, detects an error in the data, and rewrites the corrected data when the data can be corrected. About.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of a conventional memory control circuit, which is disclosed in Japanese Patent Application Laid-Open No. 6-52065. This circuit is a CPU
401, an operation mode designating circuit 402, and an address register 40 holding an address designated by an access source.
5, a data register 403 for holding the data read when the address is read, an error detection and correction circuit 404 for checking the read data and correcting a correctable error, and an error detection and correction circuit 404. It comprises a rewrite control circuit 407 for rewriting the corrected data when an error is detected, and a memory 406.

In the above configuration, when reading data from the memory 406, the memory control circuit detects an error, executes error correction if there is an error, and performs the same operation as when the corrected data is read. By performing rewriting to the address, the error data that can be corrected is prevented from progressing to the uncorrectable error data, and the reliability of the memory is improved. Also, the rewriting at this time is performed by hardware because if it is performed by software, the processing takes time.

[0004]

However, in the conventional memory control circuit as described above, when a data error is detected, control is performed so that corrected data is immediately written, and therefore, such a memory control circuit is not used. CPU at timing
When there is an access from the CPU to the memory, the CPU enters a wait state, and there is a problem that the CPU cannot immediately respond to the access from the CPU.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and if data read from a memory has an error, and if the data can be corrected, the corrected data is rewritten to the memory so that the progress of the error in the memory data can be prevented. It is another object of the present invention to prevent a rewrite operation from being in a wait state for access of an external input / output device.

[0006]

In order to achieve the above object, in a memory system according to the first aspect, data is read from a readable / writable memory, and an error in the data is detected and corrected. An error detection and correction circuit for detecting an error in data read from the memory and outputting correction data when an error is detected, and an error detection and correction circuit for detecting an error in the data read from the memory. A rewrite address register for holding the address, a rewrite data register for holding correction data output when an error is detected by the error detection and correction circuit, An address selector that selects and outputs the address output from the write address register, and data that is output externally A memory input data selector for selecting and outputting a data output from the rewrite data register, arbitrating a normal memory access request from the outside and a rewrite request for the correction data, and outputting a control signal for memory access. A memory access control circuit for outputting, and an address comparison circuit for comparing the output of the rewrite address register with the value of an address output from the outside and providing the result to the memory access control circuit.

That is, if an error is detected in the data read from the memory and the data can be corrected, the corrected data is output to an external input / output device as read data and stored in a rewrite data register. The rewritten address is stored in a rewrite address register, and a rewrite request signal for requesting the memory access control circuit to rewrite the stored correction data in the memory is output. Memory read request / memory write request from a data input / output device that performs data input / output
And a rewrite request signal are input and arbitrated so that the memory access from the input / output device is prioritized, and the access weight from the data input / output device is minimized.

Further, the memory system according to the present invention further comprises a memory output data selector for outputting a value output from the rewrite register as read data from the memory.

That is, in the first embodiment, when the memory is read and the read operation is performed from the rewrite address, the rewrite is always given priority. In the second embodiment, the memory access control circuit outputs the data from the address comparison circuit. If the comparison results match, the memory output data selector is controlled so that the output of the rewrite data register becomes read data, and read priority is given.

In the memory system according to a third aspect, the memory access control circuit outputs a memory read request signal for outputting a memory read request again.

That is, in the first embodiment, when a memory read is performed from an address other than the rewrite address, the rewrite is always given priority.
When a data error is detected at the time of memory reading, rewriting is immediately executed, and the memory access control circuit for making a memory reading request again outputs a re-memory reading request signal to give priority to reading.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory system according to the present invention will be described in detail in the order of [Embodiment 1], [Embodiment 2], [Embodiment 3] with reference to the accompanying drawings.

First Embodiment (Configuration of First Embodiment) FIG. 1 is a block diagram showing a configuration of a memory system according to a first embodiment. In the figure, reference numeral 101 denotes a readable / writable memory for storing data including a redundant bit for detecting a correctable error, and 102, a selector for selecting and outputting write data and data from a rewrite data register described later, A memory input data selector 103 for writing data is a rewrite data register for storing data output from an error detection and correction circuit described later when the data is corrected data.

Reference numeral 104 denotes an error detection and correction circuit for checking whether or not the data from the memory 101 has an error, outputting corrected data when there is an error, and outputting the data as it is when there is no error. .

A read request signal 105 or a write request signal from an external input / output device (not shown) and a rewrite request signal 105 are input to the memory 105 for arbitration.
A memory access control circuit for outputting a control signal to read or write to 01, a rewrite address register 106 for holding a value of an address to be rewritten, 106
An address selector 07 selects and outputs an address value output from an external input / output device (not shown) and a value of the rewrite address register 106 and uses it as address data to the memory 101. 108 denotes an external input / output device. This is an address comparison circuit that checks whether or not the address value output from a not-shown address matches the value of the rewrite address register 106 and outputs the result.

Although not shown, an input / output device for giving an address to the memory 101 and inputting / outputting data is externally connected.

(Operation of Embodiment 1) Next, the operation of the memory system configured as described above will be described.

First, a read operation from the memory 101 will be described. A memory read is started based on a request from the input / output device. The memory access control circuit 105
When a read access request is received from the PU, it is confirmed that a request for rewriting has not been received from the error detection and correction circuit 104, and control for reading to the memory 101 is executed.

Next, the error detection and correction circuit 104 inputs the data read from the memory 101 and checks whether there is any error. Here, an error is detected, and if it can be corrected, the corrected data is output. On the other hand, if no error is detected, the data read from the memory 101 is directly output. If an error is detected, the error detection and correction circuit 104
3 outputs a control signal for holding the correction data.

Thereafter, the error detection and correction circuit 104 outputs a rewrite request signal to the memory access control circuit 105. The memory access control circuit 105 executes rewriting and notifies the error detection and correction circuit 104 of the end of rewriting. After that, the error detection and correction circuit 104 ends the output of the rewrite request signal.

When a memory access request is not issued from the input / output device when the rewrite request signal is output, rewrite is executed.

First, the memory access control circuit 105
The memory input data selector 102 is controlled so that the value from the rewrite data register 103 is input to the memory 101. Further, the value of the rewrite address register 106 is stored in the memory 1 for the address selector 107.
01 is input. And the memory 10
1 and outputs a memory control signal at a necessary timing, and writes correction data into the memory 101.

In FIG. 1, the port for memory write data, the port for memory read, and the port for memory address are separate, but these may be common ports. .

Next, a case where a memory access request and a rewrite request from the input / output device conflict will be described.
The case where a rewrite request has occurred will be described below. In this case, the operation differs depending on whether the address desired to be accessed from the input / output device matches the address to be rewritten or not, and will be described separately.

When the address to be written to the memory coincides with the address to be rewritten, the value of the corresponding address in the memory 101 is such that new data is written.
No correction data is written, and only data is written from the input / output device.

At this time, the memory access control circuit 105
Notifies the error detection and correction circuit 104 of the end of the rewriting, thereby terminating the output of the rewriting request signal.

When the address to be written to the memory does not match the address to be rewritten, the write operation from the input / output device is prioritized to improve the processing speed for the input / output device. After the end of the write operation, a rewrite operation is started.

If the memory read address matches the rewrite address, erroneous data is
1, the correction data is written with priority given to rewriting, and a wait signal is output to the input / output device. After that, the wait signal ends and the read operation starts.

When the address to be read from the memory does not match the address to be rewritten. When an error is detected again in the data to be read, the rewrite data register 10
3 stores the previous correction data, so that new correction data cannot be written to the rewrite data register 103. Therefore, the rewrite is prioritized and a wait signal is output to the input / output device. After that, the wait signal ends and the read operation starts.

[Second Embodiment] (Configuration of Second Embodiment) FIG. 2 is a block diagram showing a configuration of a memory system according to a second embodiment. This memory system has a configuration in which a memory output data selector 201 is added to the configuration of FIG. Therefore, the other components and their functions are the same as those in FIG. 1, and therefore are denoted by the same reference numerals and description thereof will be omitted.

(Operation of Second Embodiment) Next, the operation of the memory system configured as described above will be described.
In the above-described first embodiment, when a memory read is a read from a rewrite address, the rewrite is always given priority, but in the second embodiment, the read is given priority.

That is, the memory access control circuit 105
When the comparison result output from the address comparison circuit 108 is the same, the memory output data selector 201
Is controlled so that the output of the rewrite data register 103 becomes read data. Then, the corrected data is output to the input / output device. After that, a rewrite operation is performed.

Here, the rewrite operation may be executed simultaneously with the read operation to the input / output device. The output from the error detection and correction circuit 104 is normally selected as the memory output data selector 201.

Third Embodiment (Configuration of Third Embodiment) FIG. 3 is a block diagram showing a configuration of a memory system according to a third embodiment. This memory system has a configuration in which the memory access control circuit 105 outputs a memory read request signal again as compared with the configuration of FIG. 1 described above. Therefore, the other components and their functions are the same as those in FIG. 1, and therefore are denoted by the same reference numerals and description thereof will be omitted.

(Operation of Embodiment 3) Next, the operation of the memory system configured as described above will be described.
In the first embodiment described above, when a memory read is performed from an address other than the rewrite address, the rewrite is always prioritized.
Let's put the lead first.

That is, if a data error is detected during memory reading, rewriting is immediately executed, and the memory access control circuit 105 for making a memory read request again outputs a memory read request signal. The re-memory read request signal generally uses a signal requesting re-execution in the input / output device.

[0037]

As described above, according to the memory system of the present invention, when an error is detected in the data read from the memory and the error can be corrected, the corrected data is sent to the external input / output. The data is output to the device as read data and stored in the rewrite data register. At the same time, the address where the error has occurred is stored in the rewrite address register.
It outputs a rewrite request signal requesting that the stored corrected data be rewritten in the memory, and a memory read request / memory write request from a data input / output device such as a CPU for inputting / outputting data by a memory access control circuit. , And a rewrite request signal, and arbitrates these so that the memory access from the input / output device is prioritized, and minimizes the access weight from the data input / output device. As a result, if there is an error in the data read from the memory and the data can be corrected, the progress of the error in the memory data by rewriting the corrected data to the memory can be prevented. It is possible to prevent the output device from being in the access wait state.

According to the memory system according to the present invention (claim 2), in the case of the memory read in the case of reading from a rewrite address at the time of memory read, priority is always given to rewrite. In item 2, when the comparison result output from the address comparison circuit in the memory access control circuit is the same, the memory output data selector is controlled so that the output of the rewrite data register becomes read data. Can be

According to the memory system of the present invention (claim 3), in the case of the memory read, when the memory is read from an address other than the rewrite address, the rewrite is always given priority. According to the third aspect, when a data error is detected at the time of memory reading, rewriting is immediately executed, and the memory access control circuit for re-executing the memory read request outputs a re-memory read request signal. Can be

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory system according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a memory system according to a second embodiment.

FIG. 3 is a block diagram illustrating a configuration of a memory system according to a third embodiment;

FIG. 4 is a block diagram showing a configuration of a conventional memory control circuit.

[Explanation of symbols]

 Reference Signs List 101 memory 102 memory input data selector 103 rewrite data register 104 error detection and correction circuit 105 memory access control circuit 106 rewrite address register 107 address selector 108 address comparison circuit 201 memory output data selector

Claims (3)

[Claims] 1. A memory system for reading data from a readable / writable memory, detecting an error in the data, and rewriting the corrected data when the data is correctable, detects an error in the data read from the memory. ,
An error detection / correction circuit for outputting correction data when an error is detected, a rewrite address register for holding an address when an error is detected by the error detection / correction circuit;
A rewrite data register for holding correction data output when an error is detected by the error detection and correction circuit; and an address selector for selecting and outputting an externally output address and an address output from the rewrite address register. A memory input data selector for selecting and outputting externally output data and data output from the rewrite data register; and arbitrating a normal external memory access request and an external corrective data rewrite request. , A memory access control circuit for outputting a control signal for memory access, and an address comparison circuit for comparing the output of the rewrite address register with the value of an externally output address and providing the result to the memory access control circuit And a memory system comprising: 2. The memory system according to claim 1, further comprising a memory output data selector for outputting a value output from said rewrite register as read data from a memory. 3. The memory system according to claim 1, wherein said memory access control circuit outputs a memory read request signal for outputting a memory read request again.