JP2003248594A - Data error check system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a size or cost of a device of a data error check system without declining an operation rate of data error detection and correction. <P>SOLUTION: When an error of data is detected by the data error check circuit, an arithmetic processing device executes a data correction program to correct the error. Since an data error is corrected by the data correction program (software), a size and cost can be reduced in a circuit for detecting and correcting a data error. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data error check system used in a data processing system or the like.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional data error checking system. 3 is an FPGA (Field Programmable Gate Arra) including an ECC (Error Correcting Code) circuit.
y), a large scale integrated circuit that is a programmable gate array on a substrate. The ECC circuit is a circuit for checking the normality of data, and checks whether or not the data is normally written in the memory. FPG
One end of A3 is connected to the data bus 20. Here, the number of bits of data is 16 bits. FPG
At the other end of A3, a 16-bit internal data bus 30
A 6-bit internal check bit bus 40 is connected. The internal data bus 30 is connected to the data memory 2,
The internal check bit bus 40 is the check bit memory 4
It is connected to the. In the system configured as above, when writing data from the data bus 20 to the data memory 2, the ECC circuit receives the input data and generates a check bit, the data is stored in the data memory 2, and the check bit is stored in the check bit memory 4. Written in.

When reading the data written in the data memory 2, the ECC circuit also reads the corresponding check bit from the check bit memory 4. And
The ECC circuit collates the data read from the data memory 2 with the check bit read from the check bit memory 4 to detect / correct a 1-bit error and detect a 2-bit error. Then, the data to which the data error correction process has been added is rewritten to the address where the data error is detected. As described above, in the conventional data error check system, the functional processing such as data error detection and correction is performed by hardware.

[0004]

Since the conventional ECC check function is more efficient as the number of bits is larger,
An ECC circuit corresponding to the bus size of the data bus is often formed. As a result, the number of logics in the ECC circuit increases, and a complicated auxiliary circuit is required for controlling the Read and Write signals, the access type, the memory control, etc. performed by the FPGA including the ECC circuit. Further, it is necessary to use an FPGA having a large number of logics and a large cost. Therefore, the size and cost of the hardware increase, and the size and cost of the data processing system also increase. Especially, in the case of an embedded device, it has a great influence. Further, in a microcomputer used in a PC or the like, a circuit for performing memory control is formed by an external circuit, whereas a microcomputer for an embedded device has a built-in memory control and is integrated into one chip. It is necessary to read and write data in synchronization with the operation of the microcomputer.
However, when checking the data error in the embedded device, the data is read from the memory and at the same time the EC is read.
It takes time to read the C code, detect the data error by comparing the read data with the ECC code, and perform all the ECC functions such as correcting the error portion.
It is necessary to reduce the operating speed of the microcomputer in accordance with the time required for the ECC function. If this happens, the performance of the system will decrease.

The present invention takes the above problems into consideration, and provides a data error check system capable of reducing the size or cost of the system without impairing the performance of the system.

[0006]

In the data error check system according to the present invention, a part of the data error detection / correction function is carried out by the arithmetic processing unit executing a program (software). That is, when a data error is detected, the data correction program is executed,
Data errors are corrected. Therefore, it is possible to reduce the size or cost of a circuit or device for detecting an error in data. Data error detection is performed by an ECC circuit that uses an ECC code that is a data error correction code, for example.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a data processing system including a data error checking system according to an embodiment of the present invention. CPU, which is an arithmetic processing unit that performs data processing
1 and a DATA-SDRAM 2 which is a data memory used by the CPU 1 to write / read data and used as an OS / application execution memory;
An FPGA 3 including an ECC circuit that performs ECC code creation / error detection of data written in the ATA-SDRAM 2 is connected to a data bus (Data) and a control signal system control bus (Control). In addition, FPGA3
ECC which is a memory for ECC via the ECC-Data bus
-E connected with SDRAM4 and created by ECC circuit
CC code is ECC-SDR via ECC-Data bus
It is stored in AM4. When a data error is detected by the ECC in the ECC circuit in the FPGA3, the CPU1
Reads the data correction program from the FROM5, which is a memory storing the ECC data correction program, and executes the data correction program to correct an error in the data.
Rewrite the data in ATA-SDRAM2.

As described above, in this embodiment, the data error correction is performed by the C circuit, not the ECC circuit (hardware).
Since it is performed by executing the data correction program (software) by the PU1, the scale of the ECC circuit can be reduced accordingly and the cost can be reduced. In addition, since the CPU 1 performs the correction process, the processing speed is improved, so that the error detection / correction operation function by ECC can be speeded up. In addition, the CPU 1 also has an ECC function, so that C can be adjusted according to the ECC circuit.
Since it is not necessary to slow down the operation of PU1, the operating speed of the entire data processing system can be improved. Alternatively,
Since the idle time (non-operating time) of the CPU 1 during the ECC operation is reduced, the efficiency of data processing is improved.
The data correction program is DATA-SDRAM.
Although it may be stored in the memory 2, it is more reliable to store it in the independent FROM 5 because the probability of data or software collapse is reduced.

FIG. 3 is a diagram showing the system configuration of the embodiment of FIG. 1 in more detail. The same parts as those in FIG. 1 are designated by the same reference numerals.

CPU 1 comprising a microcomputer
Is an external 32-bit data bus (D0 to D31),
It is connected to an address bus (A0 to A25) and a control signal control bus (Control). Data storage, DAT which is an OS / application execution memory
The A-SDRAM 2 is externally connected to a 32-bit data bus (D0 to D31), an address bus (A2 to A15), and a control signal control bus (Control).

The FPGA 3 including the ECC circuit is connected to the outside 32
It is connected to the bit data bus, address bus, and control signal system control bus. The data bus (D0 to D31) input to the FPGA3 improves the system safety by preventing the instruction code of the microcomputer from being converted into data. Therefore, the instruction bit of the microcomputer used is 16 bits. Therefore, in the internal ECC circuit, the internal upper data bus 6 (D0 to D0
D15) and the internal lower data bus 7 (D16 to D31) are divided into two and connected to the ECC-Data generation circuit 8. The ECC circuit in FPGA3 is an internal high-order data bus,
Both internal lower data buses have the same structure, that is, ECC-Da
ta generation circuit 8, ECC-Data check circuit 9 and EC
Since it has C-Error 10 (address detection where there is an ECC error), the internal upper data bus will be mainly described below.

At the time of writing data, ECC-Da
The ta generation circuit 8 includes an ECC-Data bus 11 (ECC0-E).
CC7). The ECC-Data bus 11 is an EC
It is connected to C-SDRAM4 and ECC-Data (E0-E
The upper ECC-Data is written in 7) and the ECC-Data
The lower ECC-Data is written in (E8 to E15).
The ECC-SDRAM 4 is an ECC-Data bus 11 (E0 to E0
E15), an address bus (A2 to A15), and a control signal control bus (Control). The ECC-SDRAM4 is the ECC-S in the FPGA3.
It is controlled by the DRAM control circuit 12.

FIG. 6A shows an E performed in the ECC-Data generating circuit 8 when writing data to each SDRAM.
A CC-Data generation method is shown. E0 to E5 are calculated according to the contents of the write data (D0 to D15), and E6 is always 0. In addition, in this embodiment, since ECC-Data is generated in units of 16 bits, By
When te-Access (8 bits) is performed, E7 is set to "0" so that the ECC check is not performed.

When reading data, ECC-
The Data bus 11 is connected to the ECC-Data check circuit 9 in the FPGA 3. Fig. 6 (2) shows E when reading data.
The ECC check method performed in the CC-Data check circuit 9 is shown. Each value of S0 to S5 and ECC-ERROR is set to read data (D
0 to D15) and reading E from the ECC-SDRAM 4
When CC-Data (E0 to E7) is calculated and S0 to S5 are all "0" and the ECC enable of E7 is "1", it is determined that there is no data error. Further, if E7 is '0', that is, if the data subjected to Byte-Access is included, no error check is performed. On the other hand, if an ECC check is performed and there is a “1” in S0 to S5, for example, if “S0, S1 ..., S5” is “101100”, that is, if a data error occurs, the microcomputer 1 Generates an ECC error interrupt. At the same time, the ECC-ERROR register 10 stores the address in which the ECC error has occurred, the internal upper data bus 6 (D0 to D15), and the internal lower data bus 7.
Error information such as in which of (D16 to D31) the error occurred is stored.

The FROM 5 is externally connected to a 32-bit data bus (D0 to D31), an address bus (A2 to A21) and a control signal control bus (Control). The FROM 5 stores a data correction program based on ECC. And CPU1 is FPG
When receiving an ECC error interrupt from A3, FR
Load and execute the data correction program from OM5,
Data correction by ECC is performed.

FIG. 7 is an error bit detection table on which data correction is based. The CPU 1 executes the data correction program stored in the FROM 5, and the ECC-ERR of the FPGA 3 is executed.
Information is retrieved from the OR register 10. At this time, ECC
-Address of ERROR register 10: 0x10000
020 is the address information at which the last ECC error occurred, and the 13th bit of the address: 0x10000024 is '1' when an ECC error occurs in the upper 16 bits of the data, and the lower 16 bits of the ECC in the 12th bit.
When an error occurs, error information "1" is stored. This error information is read and the corresponding DATA-
Data of SDRAM2, ECC of ECC-SDRAM4
Read each Data. The read data is applied to the arithmetic expression of FIG. 6, S0 to S5 are calculated, and collated with the error bit detection table of FIG. If the same data exists in the table, it can be detected that the data bit is erroneous. After the detection, the CPU 1 corrects the data and rewrites the data in the original address. For example, when "S0, S1 ..., S5" is "101100", "D2" is obtained from the table of FIG.
Therefore, the operation of inverting the D2 portion of the data read from the DATA-SDRAM 2 is performed. if,
If none of the table in FIG. 7 applies, there is an error of 2 bits or more, and since correction is impossible, only data error detection is notified. The above operation is performed by the CPU 1 by executing the data correction program.

FIG. 4 shows the flow of operations at the time of writing data in the above embodiment. CPU1 is DATA-SDR
When writing data to the AM2 (S1), the FPGA 3 divides the data into 16-bit units to create an ECC code (S2), and writes the ECC code to the ECC-SDRAM 4 (S3).

FIG. 5 shows a flow chart of the operation when reading data. When the CPU 1 reads an address, DATA
-Read the corresponding data from SDRAM2 and ECC-SDRAM4 to FPGA3, respectively (S4, S5).
After reading, the data from DATA-SDRAM2 and E
A comparison operation is performed with the ECC code from the CC-SDRAM 4 to determine whether it is correct (S6). At that time, if the read data is Byte-Access (8 bits) and the ECC code has the information, the ECC check is not performed. If an error is detected, FPGA3 becomes CPU1
An ECC error interrupt is generated at (S7). CPU
1 detects the interrupt, and executes the data correction program by the ECC stored in the FROM 5 (S
8). After that, the CPU 1 confirms the memory address where the ECC error occurs from the FPGA 3 (S9), and the data of the address is transferred to the DATA-SDRAM 2 and the ECC-SDR.
Data is read from AM4 (S10), and data correction is performed using the data correction program (S11). The data corrected is the DATA-SDR of the original address.
The data is rewritten in AM2 (S12), and the CPU1 executes ECC.
Start from the errored address reference.

According to the above-described embodiment, the number of ECC data sampling bits of the ECC circuit is reduced in units of 16 bits in the hardware to reduce the ECC circuit, and the FPGA.
It becomes possible to delete the signal control device circuits such as Write and Read inside, and the operation speed of the CPU is not limited by the ECC circuit. Therefore, the processing speed of the entire system is not impaired even though it has a data error check function. In addition, it is possible to reduce hardware costs.

[0020]

As described above, according to the present invention, the size and cost of the device of the data error checking system can be reduced without impairing the operation speed.

[Brief description of drawings]

FIG. 1 is a data processing system that is an embodiment of the present invention.

FIG. 2 shows a conventional data error checking system.

FIG. 3 shows the system configuration of FIG. 1 in more detail.

FIG. 4 is a flowchart showing an operation at the time of writing data.

FIG. 5 is a flowchart showing an operation at the time of reading data.

FIG. 6 shows an ECC data generation method and an ECC check method.

FIG. 7 is an error bit detection table.

[Explanation of symbols]

1 ... CPU, 2 ... DATA-SDRAM, 3 ... FPG
A, 4 ... ECC-SDRAM, 5 ... FROM.

Continued front page    (72) Inventor, Masateru Hosokai             1070 Ichimo, Hitachinaka City, Ibaraki Prefecture Stock Association             Hitachi, Ltd. Building Systems Group Bilso             Solution Headquarters (72) Inventor Hiroyuki Hatsawa             1070 Ichimo, Hitachinaka City, Ibaraki Prefecture Stock Association             Hitachi, Ltd. Building Systems Group Bilso             Solution Headquarters F term (reference) 5B001 AA03 AB01 AB02 AE07                 5B018 GA02 HA15 KA21 NA02 QA14                       RA01                 5J042 BA01 CA00 CA20 DA00                 5J065 AA01 AB01 AC04 AD03 AE06                       AF03 AH06

Claims (4)

[Claims] 1. A data error check circuit for detecting a data error, and when the data error check circuit detects the data error, a data correction program for correcting the data error is executed to execute the data correction program. A data error checking system comprising: an arithmetic processing unit that corrects data. 2. The arithmetic processing device according to claim 1, wherein the arithmetic processing unit writes / reads the data to / from a data memory, and is a memory different from the data memory, and stores a memory for storing the data correction program. Data error check system equipped. 3. The data error check system according to claim 1, wherein the data error check circuit detects a data error in each of upper data and lower data of the data. 4. The data error check system according to claim 1, wherein the data error check circuit detects an error in the data by an ECC code.