JPH0443447A - Rom diagnosis device - Google Patents

Abstract

PURPOSE:To miniaturize a device and to reduce cost by storing a check code through the use of RAM whose bit constitution is less than ROM. CONSTITUTION:At the time of initializing a computer system, a check code generation circuit 21 generates the check codes which respectively correspond to the storage content of ROM 12 and a RAM write circuit 24 writes the generated check code in RAM 13. Whenever ROM 12 is accessed, the check code is read from the corresponding address of RAM 13. When there is an error in the storage content which the check circuit 22 accesses, an interruption generation circuit 23 gives an interruption signal to CPU 11. Thus, not only the number of chips but also cost is reduced by using RAM instead of ROM.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application 5F) The present invention relates to a ROM diagnostic device used in a computer system using a ROM, and particularly to a ROM diagnostic device for detecting errors in stored contents of a ROM. The present invention relates to an improvement of a ROM diagnostic device for the purpose of the present invention.

(Prior art) ROM elements, EFROM (Erasable Programmable RO
M) elements are widely used, but in recent years EEPRO
M (Electrica IyEra
Sable programmable ROM) devices have also come into use. These elements are constructed as one element in units of 8 bits to 16 bits. Below, these ROM elements, EFROM elements, etc.
EPROM elements and the like are collectively called ROM.

By the way, this type of ROM self-diagnosis method is a method of self-diagnosis by comparing the checksum obtained by adding up the memory contents of the ROM from the beginning to the end with the checksum code written in the ROM in advance. be. In general, self-diagnosis using check sums is performed only once when the system is initialized, and error detection codes such as parity checks (
Hereinafter referred to as a check code) method is used.

Figure 6 shows a conventional ROM that embodies such a self-diagnosis method.
FIG. 2 is a block diagram of a diagnostic device. In the same figure, 1 is the CPU
, 2 is ROM, 3 is parity check circuit, 4 is ROM
This is a parity ROM that stores parity bits corresponding to all elements as a check code of ROM2, and is configured with a storage capacity having the same address as ROM2. Also, f is a data bus, g is a check code signal, and h
is the address bus.

(Problem to be solved by the invention) However, self-diagnosis using check sums is only performed when the computer system is initialized, and cannot detect loss of memory contents or read errors that occur during operation. . On the other hand, in the method using a check code, it is necessary to add a ROM for storing the added check code. However, since the bit configuration of a ROM chip is 8 bits or 16 bits, if the check code only requires 1 or 2 bits, the ROM chip will have more unused bits, which is uneconomical. This occupies unnecessary space and becomes an obstacle to downsizing.

The present invention was made to solve the above problems, and by using RAM instead of ROM, it is possible to reduce not only the number of chips but also the cost.
The purpose of the present invention is to provide an M diagnostic device.

[Structure of the Invention] (Means for Solving the Three Problems) In order to solve the above problems, the RAM diagnostic device according to the present invention has a method for storing error check codes in a computer system using at least a CPU and a ROM. a RAM; a check code generation circuit that generates an error check code based on the storage contents of the ROM when the computer system is initialized; a RAM write circuit that writes the generated error check code to the RAM; R
Every time the memory contents of the OM are read, an error check code is read from the corresponding RAM to check whether there are any errors in the memory contents of the ROM, and if there is an error, the CP
This configuration includes a check circuit that sends an interrupt signal to U.

(Function) Therefore, by taking such measures, the present invention has the following advantages:
When a computer system is initialized, a check code generation circuit generates check codes corresponding to the contents stored in the ROM, and then the generated check codes are written into the RAM by a RAM writing circuit. Then, each time the ROM is accessed, the corresponding R
Read the check code from the AM address, and if there is an error in the memory contents accessed by the check circuit, C
It is designed to give an interrupt signal to the PU.

(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing one embodiment of the device of the present invention, and FIG. 2 is a diagram showing a specific configuration of the ROM diagnostic circuit of FIG. 1.

In FIG. 1, 11 is a CPU, 12 is a ROM for storing program data and fixed data in advance, and 1B is a RAM for storing a check code, which has the same address as the ROM 12. 14 is ROM1
Generate a check code corresponding to the memory contents of 2 and execute RA.
When writing to M13 and accessing ROM12, R
It reads the check code written in AM6, detects an error in the accessed memory contents, and sends an interrupt 1 to CPU4.
This is a ROM diagnostic circuit that gives No. 6. 15 is an I10 port.

Next, FIG. 2 is a diagram showing the configuration of the ROM diagnostic circuit 14 of FIG. 1, and specifically, a check code generation circuit that generates a check code signal g to be added to data input from the data bus f. 21. A check circuit 22 that detects data errors from the data input from the data bus f and the check code signal g; an interrupt generation unit that sends an interrupt signal k to the CPU II when an error is detected by checking the check circuit 12; Circuit 23, RAM 13
A RAM write circuit 24 sends a write timing signal to the RAM 13, a Nant gate 25 sends a RAM read signal to the RAM 13, a Nant gate 26 outputs a RAM write signal q to the RAM 6, and the like.

0 is ROM read signal, i is check code generation circuit 2
This is a switching signal for switching between the check circuit 1 and the check circuit 22.

Next, the operation during initialization of the computer system will be explained with reference to FIG.

When the CPU II starts operating, a ROM check start routine is activated as an initialization process (step S1), and after initializing the CPU II memory address register to indicate the first address (step S2), the ROM check start routine is started as an initialization process.
The check code generation mode is set based on the switching signal l of "" (step S3). Thereafter, the contents of the memory are read out from the address of the ROM 12 pointed to by the memory address register (step S4), and a checksum calculation is executed (step S5). At the same time, the check code generation circuit 11 generates a check code for the read memory content on the data bus f according to a predetermined rule (step S6), and sends a RAM write signal q to the address of the RAM 13 pointed to by the memory address register. and write the check code (step S7). If it is not the final address (step S8), the memory address register is incremented by one (step S9), and then the process returns to step 4 and the same process is repeated. If the final address has been reached (step S8), read out the checksum code previously stored at a specific address in ROMI 2. Compare it with the checksum calculation result (step 510) and it must match (step 511). For example, RO in step S12
The process moves to the M error processing routine, and if they match, the switching signal i is set to "1", the check code generation mode is ended, and the data on the data bus f is generated based on the check code written in the RAM 13. By making use of the check circuit 22 that detects errors and the interrupt generation circuit 23, the RA
A normal check mode is set in which the M read signal is used (step 813). Thereafter, each time the ROM 12 is accessed, the check code signal g is read from the RAM 13 at the same address as the ROM 12, and the check circuit 22 checks whether there is an error in the data read from the ROM 12. If there is an error, the interrupt generation circuit 23 sends a signal to the CPU II. The interrupt signal k is sent to

Next, the check code generation timing at the time of initialization will be explained with reference to FIG.

When the ROM read signal 0 is at the "0" level, after reading the storage content Dn of the ROM 12 from the address of the ROM 12 specified by the address An on the address bus h, the check code generation circuit 21 reads the storage content Dn of the ROM 12 from the storage content Dn of the ROM 12. Generate check code gn and write the RAM specified by address An at the timing of RAM write signal q.
13.

FIG. 5 shows a timing chart for accessing the ROM in a normal running state after initialization. R.O.
When M read signal 0 is at “0” level, address bus h
Reads the storage content Dn of the ROM 12 from the address of the ROM 12 specified by the above address An, and at the same time reads the check code g of the RAM 13 specified by the same address An.
n is read out at the timing for the RAM read signal. This makes it possible to compare the storage contents Dn of the ROM 12 and the check code gn of the RAM 13 at the same address as described above.

Therefore, according to the configuration of the embodiment as described above, since the check code can be stored using the RAM 13 with a bit configuration of 8 bits or less, ROM diagnosis can be performed with a smaller number of elements than when using a ROM. can be executed.

In the above embodiment, the check code generation circuit 21 and the check circuit 22 are configured separately, but since both circuits include many common parts, they can be easily integrated.

Further, the check code is not limited to an error detecting code such as a parity code, but it is also possible to automatically correct errors in the check circuit 22 using an error correcting code such as a Hamming code. .

Furthermore, instead of ROM, EPROM.

When using EEPROM, it can be easily realized using the same configuration.

[Effects of the Invention] As described above, according to the present invention, since the check code is stored using the RAM, which has a smaller bit configuration than the ROM, it greatly contributes to miniaturization and cost reduction of the device. Furthermore, since there is no need to create a ROM for storing the check code in advance, it is economical and the time and effort required to replace the ROM can be reduced.

[Brief explanation of the drawing]

1 to 5 are shown to explain an embodiment of the ROM diagnosis device according to the present invention, and FIG.
A block diagram showing the overall configuration of the M diagnostic device, FIG.
3 is a flowchart explaining the initialization operation of the device of the present invention, FIGS. 4 and 5 are timing charts when accessing the ROM, and FIG. 6 is the configuration of the conventional device. FIG. 11...CPU, 12...ROM, 13...RA
M. 14...ROM diagnostic circuit, 15...I10 port,
21...Check code generation circuit, 22...Check circuit, 23...Interrupt generation circuit, 24...RA
M writing circuit, 25.26... Nantes gate. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 ROM address h RAM Akebono RAM Read signal ρ n An+4 An+2 Figure

Claims (1)

[Claims] In a computer system using at least a CPU and a ROM, R is used to store error check codes.
AM, a check code generation circuit that generates an error check code based on the storage contents of the ROM when the computer system is initialized, and a RAM that writes the generated error check code into the RAM.
A write circuit reads out an error check code from the corresponding RAM every time the contents of the ROM are read after initialization, checks whether there are any errors in the contents of the ROM, and sends an interrupt signal to the CPU if there is an error. A ROM diagnostic device characterized by comprising a check circuit.