JPS58168347A - Detecting circuit of synchronizing code - Google Patents

Abstract

PURPOSE:To operate a circuit stably with a simple constitution, by writing data, which corresponds to the Hamming distance between a synchronizing code and an input signal, in each address of an ROM and inputting the input signal as an address to this ROM to read out said data as a synchronizing code detection signal. CONSTITUTION:An input signal (i) including the synchronizing code is given to a shift register 2 in serial through an input terminal 1 bit by bit. The parallel output of the shift register 2 is supplied as an address input signal of an ROM 13. Data is written in the ROM13 so that data corresponding to the address of the ROM13 becomes ''1'' when the Hamming distance between individual states, which the signal stored in the shift register 2 can take, and the synchronizing code is shorter than L and said data becomes ''0'' when the Hamming distance is equal to or longer than L. Output data (d) of the ROM13 is taken out through an output terminal 4 to detect the synchronizing code with allowable bit error number L-1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization code detection circuit for detecting a synchronization code necessary to determine the reception timing of a burst in a burst communication system such as the TνMA Eiho overconfidence system. The general configuration of the @ seed circuit is shown in FIG. In the figure, (1) is the input terminal of this circuit,
(2) is a shift register for accommodating the input signal supplied through this input terminal (1), the length of which is determined by the code length of the synchronization code to be detected.

In addition, (3) receives the input signal that has been serial-parallel converted by the shift register (2), and the Hamming distance between the input signal and the synchronization code to be detected is a predetermined value υ.
a synchronization code determination circuit (4) that determines whether the pulse signal is large or small and generates an output pulse signal according to the determination result;
) is an output terminal for outputting the judgment result produced by the synchronization code judgment circuit (3) to the outside. According to this circuit, when a synchronization code is applied through the input terminal (1), a synchronization code detection signal d can be obtained at the output terminal (4) with a fixed timing relationship with the time when the synchronization code is added. .

Conventionally, there have been two concrete configurations of this type of circuit, one shown in FIG. 2 and the other shown in FIG. In Fig. 2, (5) is an analog adder/subtractor that processes the output signal pressure of the shift register (2) in an analog manner. Whether a particular one is connected to the addition terminal or the subtraction terminal is determined according to the contents of the synchronization code to be detected. Further, (6) is a voltage source for comparing the output of the analog adder/subtracter (5) with that output to determine the conditions for detecting the synchronization code, and (7) is the voltage source for comparing the output of the analog adder/subtracter (5).
) is an analog comparator that compares and determines the magnitude relationship between the output of the voltage source (6) and the output of the voltage source (6), and outputs the determination result. In Fig. 3, (8) is a code generator that generates a replica of the synchronization code to be detected, and (9) is a code generator that compares the outputs of the shift register (2) and code generator (8) bit by bit. , a comparison circuit that increments the logical value %1# when the two match, and also increments the logical value 'θ' when they do not match;
αα is 11′ indicated by the comparison result produced by the comparison circuit (9)
αυ is a data generator that generates a binary code to be compared with the output 2-code data of the parallel adder circuit (10), Q2+ is a parallel adder circuit αO This is a digital comparator that compares and determines the magnitude relationship between the double code data generated by the data generator aI and the double code data generated by the data generator aI, and the judgment result is 4. Its output is sent to the synchronous code through the output terminal (4). Next, the operation of the conventional device shown in FIGS. 2 and 3 will be explained. First, the second
In the figure, the input signal i containing the synchronization code is input $++1
1, each bit is serially applied to the shift register (2). The shift register (2) converts the input signal i into serial and parallel signals, and supplies parallel signals as many as the code length of the synchronization code to the analog adder/subtractor (5). Here, when the synchronization code is stored in the shift register (2) in advance, all the signals corresponding to the logical value '1' among the outputs of the shift register (2) are sent to the addition input terminal of the analog adder/subtractor (5). ,
All the signals corresponding to 1lil logic @i % o I are sent to the analog adder/subtractor (5) and shift register (
2). Furthermore, the output voltage corresponding to the logic value 11I of the shift register (2) is
Let it be ■・ and Vl>V・, which corresponds to
The output voltage of the analog adder/subtractor (5) is transferred to the shift register (
This corresponds to the Hamming distance between the code contained in 2), the synchronization code to be detected, and 0.

In other words, the output voltage of the adder/subtractor (5) is mVl-mV・-
/(Vl-V・). In ζζ, m is the number of '1's existing in the synchronization code, n is the number of %61s existing in the synchronization code, and j is the shift register (2)
is the Hamming distance between the code sequence contained within and the synchronous code. So, this analog adder/subtractor (5)
The output of the analog comparator (1) is compared when the output of the voltage source (6) is larger than the output of the voltage source (6).
If so, the logical value 11' is outputted, and otherwise, 'O' is outputted, and the output d is taken out to the outside through the output terminal (4). Here, the output ■ of the voltage source (6) is (mV
t-mVl-(L-1)(V,-V,))>Vt>
(mVl-mVl-t, (v, -Ve)j), the shift register (2) accommodates a code whose Hamming distance from the synchronization code to be detected is smaller than L. The purpose of detecting the synchronization code is achieved by having the logical value 'I' available at the output terminal (4) at the same time.

Next, the operation of the configuration shown in FIG. 3 will be explained. Third
The operation of the circuit shown in the figure is basically the same as that of the circuit shown in Figure 2, but whereas the configuration of Figure 2 mainly operates as an analog circuit, the configuration of Figure 3 uses digital table processing. The difference is that it has been replaced by

First, an input signal i applied through an input terminal (1) is subjected to serial-to-parallel conversion by a shift register (2), and the result is led to a comparison circuit (9). This input signal converted into parallel is sent to the output of the code generator (8) and the comparator circuit (9).
) are compared bit by bit, and as a result, the bits that are found to match are given a logic value '1', and the bits that do not match are given a logic value 'θ', leading to the parallel adder <II. It will be destroyed. By keeping the code generation circuit (8) constantly generating a replica of the synchronization code, when the code sequence stored in the shift register (2) exactly corresponds to the synchronization code, The comparison circuit (9) has a logical value 11' corresponding to the code length of the synchronization code.
, and when the code sequence stored in the shift register (2) has a Hamming distance P with respect to the synchronous code, ゛ is 2
This results in logical values '0#' and (m+n-p) logical values 11'. Next, the parallel adder αα converts the plurality of input signals into a code representing the number of logical values 111 present in the plurality of input signals, for example, a double code. This code is connected to the code generated by the data generator αυ by a digital comparator α
When the former is larger than the latter, the digital comparator ■ outputs a logical value '1', otherwise it outputs a logical value 10', and the output d is sent to the output terminal. (4) Export it to the outside. By setting the code so as to correspond to the code m-)n-L generated by Komude Data Generator Co., Ltd., the scanning distance from the synchronization code to be detected is set in the shift register (2). is L
When a smaller code is accommodated, a logical value 11' is obtained at the output terminal (4), and the purpose of synchronous code detection is achieved.

Since the conventional synchronization code detection circuit is configured as described above, the one in Fig. 2 has the advantage of having fewer components. The disadvantage is that it is easy to cause instability in operation due to changes in element characteristics over time and changes in temperature and power supply voltage.
Contrary to the configuration shown in FIG. 2, the circuit configuration is complicated and has a large number of components, so there are problems in both cases.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to store data corresponding to the synchronization code detection conditions at each address of a large-capacity read-only memory that has recently become practical due to advances in semiconductor technology. The system writes the input signal sequence to this read-only memory, addresses the input signal sequence, and reads out the above data as a synchronization code detection signal. The purpose of the present invention is to provide a synchronization code detection circuit that is free from such problems.

An embodiment of the present invention will be described below with reference to the drawings. Fourth
The figure shows a synchronization code detection circuit according to an embodiment of the present invention. In the figure, (1) is an input terminal, and an input signal sequence containing the same code to be detected is applied from the outside through this terminal (1). (2) is a shift register,
It has a stage t2 equal to the code length of the synchronization code, and the input signal 1 applied through the input terminal (1) is serial-parallel converted by this shift register (2). αj is a read-only memory (hereinafter referred to as ROM) in which data corresponding to the synchronization code detection condition is written at each address, and the output of the shift register (2) is applied to its address input terminal.

Note that this ROM (13 has a 2-word robit/word configuration. In this case, k indicates the code length of the synchronization code. (4) is the output terminal, and the output data d of 10M1l is connected to this terminal (4). Afterwards, it is taken out to the outside.

Next, the operation of the apparatus shown in FIG. 4 will be explained. First, an input signal i containing a synchronization code is serially applied one bit at a time to a shift register (2) through an input terminal (1). This shift register (2) converts the input signal series into serial and parallel signals, and the parallel signals obtained as a result are stored in the ROM.
Provided as address input signal for Q3. RO* (
13 provides as output data the contents of the word specified by its address input signal. As explained earlier, the number of stages of the shift register (2) is k, and 110
Since the word capacity of MC13 is barred, the shift register (
2) For all of the states (the number of which is equal to -) that can be indicated by the signal contained in the signal, there is an address of kOMG3 corresponding to each state indicated by the signal, and the data of the word corresponding to that address is exist. Therefore, for each of the - states that the signal stored in the shift register (2) can take, the Hamming distance between it and the synchronization code to be detected is calculated, and if the distance is smaller than L, the state is The data in the word corresponding to the address of ROM Q3 becomes 11', and when the distance is equal to or greater than L, the data in the word corresponding to the address of ROM Q31 becomes 'ON'. (If you load the data into 131,
When the Hamming distance between the shift register (2) and the synchronization code is smaller than L, that is, a code similar to the synchronization code to a predetermined degree of detail is stored in the shift register (2), the output data d of ROM (13) is stored in the shift register (2). When the signal becomes I' and other signals are stored in the shift register (2), the ROM Q3) provides an output 'θ'. So ROM Q3
By outputting the output data d to the outside through the output terminal (4), it can be used as a synchronization code detection circuit with an allowable bit error number t-1.

In addition, although ROM is used as the memory in the above embodiment,
Random access memory (hereinafter referred to as RAM) may be used instead of ROM. In this case, it is necessary to write necessary data into the RAMK before using the synchronization code detection circuit, but in general, RAM has the advantage of being able to operate at high speed more easily than kOM. Furthermore, although the embodiment has been described with respect to one reception channel to which a synchronization code is provided, the present invention can also be applied to a case where a synchronization code is provided through two or more parallel channels as shown in FIG. The fifth V shows an example in which the synchronization codes !a, ib are applied through two input terminals (1b).

Note that (21X2b) in the figure is a shift register, respectively.

As described above, according to the present invention, the synchronization code is detected by reading out the input signal sequence as an address input from the ROM in which the synchronization code detection conditions are written in advance, so that the operation based on analog operation is possible. This has the effect of providing an IbJ period code detection circuit which does not have the problem of instability and has a simple configuration with a small number of components.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the general configuration of a synchronization code detection circuit, Figures 2 and 3 are circuit diagrams showing the configuration of a conventional σ synchronization code detection circuit, and Figure 4 is a block diagram showing the configuration of a conventional σ synchronization code detection circuit. FIG. 5 is a circuit diagram showing the configuration of a synchronization code detection circuit, and FIG. 5 is a circuit diagram showing the configuration of another embodiment that supports multiple inputs. (2)...Shift register, Q3...ROM. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Makoto Kuzuno - Figure 1 Figure 211! 11 Figure 3m Figure 4

Claims (1)

[Claims] (1) A shift register that receives an input signal sequence including a synchronous code sequence and converts the input signal sequence into serial to parallel, and a shift register that stores nine data corresponding to the synchronous code detection condition at each address, A synchronous code detection circuit comprising: a read-only memory that outputs stored data at an address determined by an input parallel signal as a synchronous code detection signal.