JPS54108546A - Converter for information array - Google Patents

Converter for information array

Info

Publication number
JPS54108546A
JPS54108546A JP1523078A JP1523078A JPS54108546A JP S54108546 A JPS54108546 A JP S54108546A JP 1523078 A JP1523078 A JP 1523078A JP 1523078 A JP1523078 A JP 1523078A JP S54108546 A JPS54108546 A JP S54108546A
Authority
JP
Japan
Prior art keywords
information
memory
stored
array
pieces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1523078A
Other languages
Japanese (ja)
Inventor
Shunichi Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1523078A priority Critical patent/JPS54108546A/en
Publication of JPS54108546A publication Critical patent/JPS54108546A/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE: To make it possible to change an array of information at random by rotating address codes by the fixed number of bits and also by rearranging the updated address codes.
CONSTITUTION: Cards in certain array order (a) is divided (b) into two and both groups of cards are combined (c) alternately. Namely, shuffling playing cards is equivalent, with information composed of eight pieces, to transferring pieces of information D1, D2,...D8 stored in memory 1 into memory 2 in the order of D1, D5, D2,...D8 electrically. To realize this operation without using a sorting method of the kind next, pieces of information D1 to D8 with address codes AC added are stored and arranged in memory 11 in sequence and each information read out is stored in data buffer 12 while its AC is in address control circuit 13 and then rotated by one bit ([011] changes into [110]) before the information is transferred to memory 14 and rearranged. In this way the conversion of an array of information is realized.
COPYRIGHT: (C)1979,JPO&Japio
JP1523078A 1978-02-13 1978-02-13 Converter for information array Pending JPS54108546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1523078A JPS54108546A (en) 1978-02-13 1978-02-13 Converter for information array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1523078A JPS54108546A (en) 1978-02-13 1978-02-13 Converter for information array

Publications (1)

Publication Number Publication Date
JPS54108546A true JPS54108546A (en) 1979-08-25

Family

ID=11883052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1523078A Pending JPS54108546A (en) 1978-02-13 1978-02-13 Converter for information array

Country Status (1)

Country Link
JP (1) JPS54108546A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60204032A (en) * 1984-03-28 1985-10-15 Res Dev Corp Of Japan Pseudo random number generating circuit
JPH0736671A (en) * 1993-07-19 1995-02-07 Nec Corp Data rearranging method and data rearranging device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60204032A (en) * 1984-03-28 1985-10-15 Res Dev Corp Of Japan Pseudo random number generating circuit
JPH0736671A (en) * 1993-07-19 1995-02-07 Nec Corp Data rearranging method and data rearranging device

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