JPS5583939A - Microprogram control processor - Google Patents

Microprogram control processor

Info

Publication number
JPS5583939A
JPS5583939A JP15639778A JP15639778A JPS5583939A JP S5583939 A JPS5583939 A JP S5583939A JP 15639778 A JP15639778 A JP 15639778A JP 15639778 A JP15639778 A JP 15639778A JP S5583939 A JPS5583939 A JP S5583939A
Authority
JP
Japan
Prior art keywords
register
bits
output
specific field
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15639778A
Other languages
Japanese (ja)
Inventor
Haruyuki Furukawa
Masato Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15639778A priority Critical patent/JPS5583939A/en
Publication of JPS5583939A publication Critical patent/JPS5583939A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To secure the effect identical to the substantial extension of the bit number without giving extension to the bit number in the specific field by giving decoding to the bits in the specific field in coincidence with the several bits of the address register which holds the address of one microorder word provided separately and under excecution.
CONSTITUTION: Delay latch 105 sets two bits within address register 100 in the same timing as data register 106. Register 106 holds one microorder word under being processed and then sets the output of selection circuit 104. Decoder circuit plus decoding selection circuits 107W110 switch for output the decode of 3 bits in the specific field of register 106 into four kinds via the output of two bits of latch 105. Several bits among the output of register 106 are sent to register 100, and other several bits are sent to test matrix 106 each. Figures 101 and 102 show the control memory devices.
COPYRIGHT: (C)1980,JPO&Japio
JP15639778A 1978-12-20 1978-12-20 Microprogram control processor Pending JPS5583939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15639778A JPS5583939A (en) 1978-12-20 1978-12-20 Microprogram control processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15639778A JPS5583939A (en) 1978-12-20 1978-12-20 Microprogram control processor

Publications (1)

Publication Number Publication Date
JPS5583939A true JPS5583939A (en) 1980-06-24

Family

ID=15626835

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15639778A Pending JPS5583939A (en) 1978-12-20 1978-12-20 Microprogram control processor

Country Status (1)

Country Link
JP (1) JPS5583939A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02178836A (en) * 1988-12-29 1990-07-11 Casio Comput Co Ltd Central arithmetic processing unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02178836A (en) * 1988-12-29 1990-07-11 Casio Comput Co Ltd Central arithmetic processing unit

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