JPS5624843A - Bit phase control circuit - Google Patents

Bit phase control circuit

Info

Publication number
JPS5624843A
JPS5624843A JP10017479A JP10017479A JPS5624843A JP S5624843 A JPS5624843 A JP S5624843A JP 10017479 A JP10017479 A JP 10017479A JP 10017479 A JP10017479 A JP 10017479A JP S5624843 A JPS5624843 A JP S5624843A
Authority
JP
Japan
Prior art keywords
clock
level
data signal
control circuit
multiphase clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10017479A
Other languages
Japanese (ja)
Other versions
JPS598104B2 (en
Inventor
Shuji Kimura
Eiji Inishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54100174A priority Critical patent/JPS598104B2/en
Publication of JPS5624843A publication Critical patent/JPS5624843A/en
Publication of JPS598104B2 publication Critical patent/JPS598104B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To secure the matching with the same phase among the changing points of the signal, by generating the multiphase clock after extracting the clock out of the data signal and then securing the decision by majority for the level output of the data signal corresponding to the generating timing of the multiphase clock. CONSTITUTION:The multiphase clock is generated from multiphase clock generating circuit 3 to which delaying circuits 31-35 are connected in series. The level of data signal S1 at the moment of the rise of each clock is stored in flip flops 41-45 each. With the rise of clock phi6, the decision by majority is secured for the output contents of flip flops 41-45. Then the level is decided for output signal Sa.
JP54100174A 1979-08-08 1979-08-08 Bit phase adjustment circuit Expired JPS598104B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54100174A JPS598104B2 (en) 1979-08-08 1979-08-08 Bit phase adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54100174A JPS598104B2 (en) 1979-08-08 1979-08-08 Bit phase adjustment circuit

Publications (2)

Publication Number Publication Date
JPS5624843A true JPS5624843A (en) 1981-03-10
JPS598104B2 JPS598104B2 (en) 1984-02-22

Family

ID=14266948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54100174A Expired JPS598104B2 (en) 1979-08-08 1979-08-08 Bit phase adjustment circuit

Country Status (1)

Country Link
JP (1) JPS598104B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6051339A (en) * 1983-07-11 1985-03-22 インタ−ナシヨナル　スタンダ−ド　エレクトリツク　コ−ポレイシヨン Arrival time instructing device of receiving signal
JPS61231395A (en) * 1985-04-03 1986-10-15 Kajima Corp Heat-accumulating tank
EP0208449A2 (en) * 1985-06-21 1987-01-14 Advanced Micro Devices, Inc. Apparatus for synchronization of a first signal with a second signal
JPS628572U (en) * 1985-06-26 1987-01-19
JP2007174023A (en) * 2005-12-20 2007-07-05 Hitachi Information & Communication Engineering Ltd Clock synchronizing method and clock synchronizing circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6051339A (en) * 1983-07-11 1985-03-22 インタ−ナシヨナル　スタンダ−ド　エレクトリツク　コ−ポレイシヨン Arrival time instructing device of receiving signal
JPH0577990B2 (en) * 1983-07-11 1993-10-27 Int Standard Electric Corp
JPS61231395A (en) * 1985-04-03 1986-10-15 Kajima Corp Heat-accumulating tank
EP0208449A2 (en) * 1985-06-21 1987-01-14 Advanced Micro Devices, Inc. Apparatus for synchronization of a first signal with a second signal
JPS628572U (en) * 1985-06-26 1987-01-19
JP2007174023A (en) * 2005-12-20 2007-07-05 Hitachi Information & Communication Engineering Ltd Clock synchronizing method and clock synchronizing circuit

Also Published As

Publication number Publication date
JPS598104B2 (en) 1984-02-22

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