JPS5769594A - Holding mode current reducing circuit of semiconductor circuit - Google Patents

Holding mode current reducing circuit of semiconductor circuit

Info

Publication number
JPS5769594A
JPS5769594A JP55143321A JP14332180A JPS5769594A JP S5769594 A JPS5769594 A JP S5769594A JP 55143321 A JP55143321 A JP 55143321A JP 14332180 A JP14332180 A JP 14332180A JP S5769594 A JPS5769594 A JP S5769594A
Authority
JP
Japan
Prior art keywords
circuit
holding mode
clock
power consumption
holding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55143321A
Other languages
Japanese (ja)
Inventor
Minejiro Nojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55143321A priority Critical patent/JPS5769594A/en
Publication of JPS5769594A publication Critical patent/JPS5769594A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/04—Shift registers

Landscapes

  • Logic Circuits (AREA)
  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To obtain a circuit which is capable of reducing the power consumption in case of a holding mode without givng a hindrance to operation of a dynamic circuit, by changeover a clock to the dynamic circuit, to a low speed clock in accordance with a holding or regular mode. CONSTITUTION:When a holding mode signal becomes a high level and a hoding mode is selected, AND gates 24, 26 of a clock selecting circuit 23 are opened and closed, respectively, by the holding mode signal and the holding mode signal through an inverter 25. Subsequently, a clock applied to a dynamic shift register 28 from an NOR circuit 27 is charged over from a high speed clock to a low speed clock passing through a frequency divider 22, and its operating speed is lowered, but the register 28 is operated exactly by small power consumption. Also, a timing signal is not generated from a timing generator 29 by a high level holding mode signal, a static circuit is not operated, and the power consumption is reduced. In this way, it is possible to obtain a circuit which is capable of reducing the power consumption in case of a holding mode without giving a hindrance to operation of a dynamic circuit.
JP55143321A 1980-10-14 1980-10-14 Holding mode current reducing circuit of semiconductor circuit Pending JPS5769594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55143321A JPS5769594A (en) 1980-10-14 1980-10-14 Holding mode current reducing circuit of semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55143321A JPS5769594A (en) 1980-10-14 1980-10-14 Holding mode current reducing circuit of semiconductor circuit

Publications (1)

Publication Number Publication Date
JPS5769594A true JPS5769594A (en) 1982-04-28

Family

ID=15336059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55143321A Pending JPS5769594A (en) 1980-10-14 1980-10-14 Holding mode current reducing circuit of semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS5769594A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184826A (en) * 1982-04-22 1983-10-28 Matsushita Electric Ind Co Ltd Logical function circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184826A (en) * 1982-04-22 1983-10-28 Matsushita Electric Ind Co Ltd Logical function circuit

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