JP2022159932A - direct digital synthesizer - Google Patents

Abstract

To provide a direct digital synthesizer capable of obtaining a resolution below a reference frequency without changing waveform data.SOLUTION: A direct digital synthesizer includes a waveform conversion processing unit in which one cycle of waveform data is stored corresponding to a predetermined number Mo of address data, an accumulation processing unit that performs overflow processing using an overflow set value on the basis of an accumulated processing value obtained by accumulating frequency set values, and an address conversion processing unit that outputs the address data on the basis of the accumulated data obtained from the accumulated processing value for the number of significant digits of the overflow setting value corresponding to the number of digits of Mo, and the waveform conversion processing unit outputs the waveform data corresponding to the address data output from the address conversion processing unit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a direct digital synthesizer (hereinafter abbreviated as "DDS") used in wireless communication equipment and the like, and more particularly to a direct digital synthesizer capable of obtaining a resolution of a reference frequency or less.

In the field of wireless communication equipment, DDS is widely used as high-frequency signal generating means. A conventional DDS includes a phase accumulator 100, a sine wave conversion table 101, and a digital/analog converter (hereinafter abbreviated as “DAC”) 102, as shown in FIG. The phase accumulator 100 includes, for example, an adder and a latch circuit. Each time the clock signal CL is input to the latch circuit, the adder accumulates the accumulated value until the accumulated value of the adder reaches the overflow set value. It is designed to overflow at the timing of Therefore, a sawtooth-shaped output signal corresponding to the overflow set value is output. Waveform data relating to a sine wave is written in the sine wave conversion table 101, and the waveform data of the sine wave is obtained by reading out the waveform data using the accumulated value of the adder as an address and converting the data by the DAC. become. The obtained waveform data is formed in steps corresponding to the clock signal at a frequency corresponding to the frequency setting value, and a sine wave waveform from which the clock component is removed is output by using a filter circuit such as a low-pass filter. be able to.

As such a DDS, for example, Japanese Unexamined Patent Application Publication No. 2002-200000 discloses data input to a latch according to an output signal of a comparator that compares an arbitrary integer M given from the outside with output data A=K+D of a full adder. A frequency synthesizer is described that forces the rewriting of to make it behave like an overflow at an arbitrary threshold M. Further, Patent Document 2 discloses a numerically controlled oscillator that divides an output from an accumulator that adds a phase signal by a fixed integer value M using a divider, and outputs an output signal from a lookup table based on the divided output signal. Have been described.

JP-A-10-116181 JP-A-2000-252750

In a conventional DDS, the phase accumulator has an overflow value of 2 ⁿ when the adder consists of n bits, so the frequency resolution is 1/2 ⁿ , and the frequency of the output signal may not be set accurately. occur. For example, n=10 would result in a phase accumulator with an overflow value set to 1024. When the frequency of the clock signal is 1 kHz and the additional value Δ per clock is 100, the output frequency is obtained as follows.
1000Hz x 100/1024 = 97.65625Hz
Therefore, the output frequency cannot be set exactly at 100 Hz. Therefore, when outputting 100 Hz, the output frequency is set to 100 Hz by alternately outputting the output signals at Δ = 102 (output frequency; 99.609375 Hz) and Δ = 103 (output frequency; 100.5859375 Hz) at a constant ratio. is approximated to However, it is inevitable that the output frequency fluctuates.

In Patent Document 1, the output frequency is adjusted by processing the output from the adder, but if the set value M is changed, waveform data corresponding to it is required to operate with the same hardware. , there is a problem in achieving practical use.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a direct digital synthesizer capable of obtaining a resolution equal to or lower than a reference frequency without changing waveform data.

A direct digital synthesizer according to the present invention includes a waveform conversion processing unit in which one cycle of waveform data is stored corresponding to a predetermined _number of address data, and based on an accumulated processed value obtained by accumulating frequency setting values. and an accumulating section for performing overflow processing based on the overflow set value, and the address data based on the accumulated data obtained from the accumulated processing value for the number of significant significant digits of the overflow set value corresponding to the number of digits of _Mo. and the waveform conversion processing unit outputs the waveform data corresponding to the address data output from the address conversion processing unit. Further, the accumulating section performs overflow processing with an overflow setting value M _max , and the address conversion processing section divides the accumulating processed value by (M _max /M _o ) to obtain the above Cumulative data are obtained. Further, the address conversion processing unit includes a high-order phase accumulator corresponding to the number of high-order significant digits, and the accumulation processing unit includes a low-order phase accumulator corresponding to the number of digits other than the number of high-order significant digits. and the lower phase accumulator compares the lower accumulated value obtained by accumulating the lower frequency set value with the lower overflow set value, which is the overflow set value, so that the lower accumulated value is If it is equal to or greater than the lower overflow set value, it outputs the lower carry-up data, and the upper phase accumulator stores accumulated data obtained by accumulating the upper frequency set value and the lower carry-up data as the overflow value _Mo. When the accumulated data is smaller than the _overflow value _Mo , the accumulated data is output as the address data. Output as the address data. Further, the accumulating section corrects the waveform data based on the lower-side accumulated value in the lower-side phase accumulator when the lower-side accumulated value is smaller than a lower-side overflow setting value. to output Further, the address conversion processing unit includes a high-order side phase accumulator corresponding to the number of high-order significant digits, and the accumulation processing unit corresponds to the number of high-order digits out of the number of digits other than the number of high-order significant digits. and a low-order phase accumulator corresponding to the number of low-order digits other than the number of high-order digits out of the number of digits other than the number of high-order significant digits, wherein the low-order phase accumulator is configured for the low-order frequency setting. The lower accumulated value obtained by accumulating the value is compared with the lower overflow set value among the overflow set values, and if the lower accumulated value is equal to or greater than the lower overflow set value, the lower side is carried up. and the middle-order phase accumulator uses the middle-order accumulated processing value obtained by accumulating the middle-order frequency set value and the lower-order carry-up data as the middle-order overflow set value among the overflow set values. In comparison, when the middle-order accumulated process value is equal to or greater than the middle-order overflow set value, middle-order carry-up data is output, and the upper-order phase accumulator outputs the upper-order frequency set value and the middle-order overflow set value. The accumulated data obtained by accumulating the side-carried data is compared with the overflow value _Mo , and if the accumulated data is smaller than the overflow value _Mo , the accumulated data is output as the address data, and the accumulated data overflows. If it is equal to or greater than the value _Mo , the difference between the two is output as the address data. Further, it has a phase modulation processing section that changes the phase amount of the waveform data to be output.

With the configuration as described above, the present invention provides an accumulated value obtained from the accumulated value for the number of upper significant digits of the overflow set value corresponding to the number of digits of the number M _o of the address data of the waveform conversion processing section. Since the address data is output based on the calculated data, a resolution equal to or lower than the reference frequency can be obtained without changing the waveform data.

1 is a block diagram showing the basic configuration of a direct digital synthesizer according to the present invention; FIG. FIG. 10 is an explanatory diagram relating to processing for obtaining accumulated data from accumulated processed values; FIG. 3 is a block configuration diagram in which accumulation processing and address conversion processing are performed by connecting a plurality of phase accumulators; 4 is a block configuration diagram showing a circuit configuration regarding a phase accumulator used in the processing shown in FIG. 3; FIG. FIG. 4 is a block diagram of a circuit configuration for further improving resolution when using multiple phase accumulators; FIG. 4 is a block configuration diagram of a circuit configuration that achieves resolution corresponding to rational fractions using three phase accumulators; 1 is a block diagram showing the configuration of a direct digital synthesizer including a phase modulation processing section; FIG. 3 is a block diagram showing a circuit configuration of a phase modulation processing section 70; FIG. 6 is a block diagram relating to an example in which a phase modulation processing unit is connected to the DDS shown in FIG. 5; FIG. 7 is a block diagram relating to an example in which a phase modulation processing unit is connected to the DDS shown in FIG. 6; FIG. 1 is a block diagram showing a basic configuration of a conventional DDS; FIG.

An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the embodiments described below are preferred specific examples for carrying out the present invention, and thus various technical limitations are made, but the present invention is particularly limited in the following description. These forms are not intended to be limiting unless specified.

FIG. 1 is a block diagram showing the basic configuration of a direct digital synthesizer according to the present invention. DDS is calculated by a setting processing unit 10 for setting an overflow set value M _max and a frequency set value M _inc , an accumulation processing unit 20 for performing accumulation processing based on the data set by the setting processing unit 10, and an accumulation processing. an address conversion processing unit 30 for obtaining accumulated data from the accumulated values, a waveform conversion processing unit (LUT) 40 in which waveform data for one period is stored corresponding to a predetermined number M _o of address data, and a digital A /analog conversion processing unit (DAC) 50 is provided, and the waveform conversion processing unit 40 outputs waveform data corresponding to the address data output from the address conversion processing unit 30. FIG.

The accumulation processing unit 20 includes at least one phase accumulator, and determines the input timing of the clock signal CL of the reference frequency fs based on the overflow setting value M _max and the frequency setting value M _inc set in the setting processing unit 10. The frequency setting value M _inc is accumulated every time, and the accumulated processing value M is output at each input timing.

The accumulation processing unit 20 compares the accumulation processing value M with the overflow set value _Mmax , and when the accumulation value M is small, outputs the accumulation value M as it is, and the accumulation processing value M is equal or large. In this case, the difference value is output as the accumulated processed value M. Further, as will be described later, when a plurality of phase accumulators are provided, the carry-up data is output to the higher-order phase accumulator when the accumulated value M is equal or greater.

The address conversion processing section 30 obtains accumulated data from the accumulated processing value calculated by the accumulation processing, and outputs the address data to the waveform conversion processing section 40 .

FIG. 2 is an explanatory diagram of the process of obtaining accumulated data from accumulated processed values. In this example, the overflow setting value M _max =10 ¹⁰ is used, and specific accumulated values are expressed in binary, decimal and hexadecimal numbers. Also, the number of address data in the waveform conversion processing unit is M _o =1,000, the address data takes decimal values from 0 to 999, and the specific address data is expressed in decimal and binary numbers. . Therefore, by dividing 10 ¹⁰ , which is the maximum value of the accumulated process value, by 1,000, it is possible to correspond to the address data.

When processing division into 1,000, as shown in FIG. 2, the process of acquiring accumulated data from the accumulated processed value for the number of significant significant digits of the overflow set value corresponding to the number of digits of the number of address data. can obtain accumulated data corresponding to the address data. In this example, the number of digits of the address data is 3 digits. , it is possible to obtain data corresponding to the address data.

Therefore, when the accumulated value is a binary number, it is converted into a decimal number, and the number of significant significant digits in the decimal number can be obtained as address data.

As a specific process for obtaining accumulated data from the accumulated processing value M for the upper significant digits of the overflow set value _Mmax , which corresponds to the number of digits of the number of address data M _o , the accumulated processing value M is ( M _max /M _o ) to obtain accumulated data L. A specific calculation formula is as follows.
L=M/( _Mmax / _Mo )
By performing such address conversion processing, it becomes possible to perform processing in decimal numbers, and the resolution of the reference frequency can be improved. In the example above,
M _max /M _o =10 ¹⁰ /10 ³ =10 ⁷
By dividing the accumulated value M by 10 ⁷ , the accumulated data for the upper three digits, which is the number of upper significant digits, can be obtained. When the frequency setting value M _inc is set as decimal number data, the cumulative processing value M obtained by accumulating the frequency setting value M _inc becomes decimal number data. A decimal output frequency can be set, allowing improved resolution relative to the decimal reference frequency.

Accumulated data can also be obtained without performing such division processing. FIG. 3 is a block configuration diagram for performing accumulation processing and address conversion processing by connecting a plurality of phase accumulators. FIG. 4 is a block diagram showing the circuit configuration of the phase accumulator used for such processing.

The phase accumulator P comprises an adder 20a, a subtractor 20b, a switch 20c, an overflow detector 20d and a latch circuit (FF) 20e. The adder 20a is connected to an input terminal 20g to which the frequency setting value Δ set by the setting section is input and to an input terminal 20h to which the carry-up data C output from another phase accumulator is input. The addition value (M+Δ+C) obtained by adding the frequency setting value Δ and the carry-up data C to the cumulative processing value M input from 20e is output. The subtractor 20b is connected to an input terminal 20i to which the set overflow value M _max is input by the setting unit, and _obtains a subtraction value ( M+Δ+C−M _max ).

The switch 20c latches either the addition value (M+Δ+C) output from the adder 20a or the subtraction value (M+Δ+C−M _max ) output from the subtractor 20b based on the detection signal from the overflow detector 20d. Switching processing is performed so as to input to the circuit 20e. The overflow detector 20d outputs a detection signal indicating whether the addition value (M+Δ+C) output from the adder 20a is smaller than the overflow set value _Mmax or equal to or greater than the overflow set value _Mmax . 20c. Then, when it is equal to or greater than the overflow set value _Mmax , the carry-up data C is output from the output terminal 20k to another phase accumulator.

When the detection signal from the overflow detector 20d is smaller than the overflow set value _Mmax , the switch 20c switches to the output side of the addition value (M+Δ+C) and is equal to or greater than the overflow set value _Mmax . In this case, switching processing is performed to output the subtraction value (M+Δ+C−M _max ).

The latch circuit 20e is connected to an input terminal 20f to which the clock signal CL is input, and receives the addition value (M+Δ+C) or the subtraction value (M+Δ+C−M _max ) input from the switch 20c as the input clock signal CL. is output as accumulated data L or accumulated processed value M at the input timing of . The output accumulated data L or accumulated processed value M is output to the outside from the output terminal 20j and is input to the adder 20a so that addition processing by the adder 20a is repeatedly performed.

In the example shown in FIG. 3, two such phase accumulators are used, a high-order phase accumulator P1 corresponding to the number of high-order significant digits, and a low-order phase accumulator P1 corresponding to the number of digits other than the number of high-order significant digits. It has P2. Then, they are connected so that the carry-up data C2 outputted from the lower side phase accumulator P2 is inputted to the upper side phase accumulator P1. In this case, the upper side phase accumulator P1 performs address conversion processing, and the lower side phase accumulator P2 performs accumulation processing.

The lower-side phase accumulator P2 compares the accumulated processed value M2 obtained by accumulating the frequency set value M2 _inc with the overflow set value M2 _max , and if the accumulated processed value M2 is equal to or greater than the overflow set value M2 _max , it is carried up. Output data C2.

The upper-side phase accumulator _P1 is set with an overflow value M 0 corresponding to the number of upper significant digits as an overflow set value M1 _max . Then, the accumulated data L obtained by accumulating the frequency set value M1 _inc and the carry-up data C2 is compared with the overflow value _Mo , and if the accumulated data L is smaller than the overflow value _Mo , the accumulated data L is addressed. If the accumulated data L is equal to or greater than the overflow value _Mo , the difference between the two is output as address data.

The lower-side phase accumulator P2 is designed to output the carry-up data C2=1 by overflow processing. Therefore, adding the carry-up data C2 to the upper-side phase accumulator P1 causes an overflow of the lower-side phase accumulator P2. The processing is equivalent to adding the set value M2 _max . Therefore, assuming a composite phase accumulator Pc obtained by combining the two phase accumulators P1 and P2, the composite frequency setting value Mc _inc and the composite overflow setting value Mc _max can be expressed by the following equations.
Mc _inc =M1 _inc ×M2 _max +M2 _inc
Mc _max =M _o ×M2 _max

The number of clocks nc required for one cycle of the synthetic phase accumulator Pc is
nc= _Mcmax / _Mcinc =( _Mo * _M2max )/( _M1inc * _M2max + _M2inc )
Assuming that the output period Tc of the accumulated data output from the combined accumulator Pc is the reference period Ts,
Tc = Ts x nc
can be found at Therefore, assuming that the output frequency fc of the accumulated data is the reference frequency fs,
fc=1/Tc=1/(Ts×nc)=fs×( _M1inc × _M2max + _M2inc )/( _Mo × _M2max )
can be found at Therefore, by setting the frequency setting value and overflow setting value of the upper side phase accumulator P1 and the lower side phase accumulator P2 corresponding to the desired output frequency, it is possible to output waveform data at the desired frequency.

By using such a plurality of phase accumulators, one phase accumulator can be set corresponding to the number of address data of the waveform conversion processing section and used together with another phase accumulator to improve resolution. Therefore, by combining a plurality of phase accumulators according to the purpose, it is possible to construct a DDS having various functions such as improvement of resolution of waveform data and improvement of distortion characteristics in addition to improvement of phase resolution.

FIG. 5 is a block diagram of a circuit configuration for further improving resolution when multiple phase accumulators are used. In this example, in the configuration shown in FIG. 3, the correction data conversion processing section 60 is connected to the output side of the lower side phase accumulator P2 to generate correction data for the waveform data output from the waveform conversion processing section 40. ing.

The waveform conversion processing unit 40 outputs sin θ ₁ and cos θ ₁ as waveform data, and the correction data conversion processing unit 60 corrects based on the accumulated processed value M2 output from the lower side phase accumulator P2. Data sin θ ₂ and cos θ ₂ are output. In this example, the correction data conversion processing section 60 can calculate the correction data as follows.

Since the maximum value of θ ₂ is 1/M _o of the maximum value 2π of θ ₁ based on the relationship between the two phase accumulators described above, θ ₂ is obtained by the following equation.
θ ₂ =2π×(1/M _o )×(M2/M2 _max )
The correction data sin θ ₂ and cos θ ₂ can be calculated by the following approximate expressions based on series expansion.
sin θ ₂ = θ ₂ - θ ₂ ^3/3 !
cos θ ₂ =1−θ ₂ ² /2!
By using the correction data, the waveform data can be corrected as follows.
sin (θ ₁ + θ ₂ ) = sin θ ₁ × cos θ ₂ + cos θ ₁ × sin θ ₂
= sin θ ₁ × (1−θ ₂ ² /2!) + cos θ ₁ × (θ ₂ − θ ₂ ³ /3!)
cos (θ ₁ + θ ₂ ) = cos θ ₁ × cos θ ₂ + sin θ ₁ × sin θ ₂
= cos θ ₁ × (1 - θ ₂ ² /2!) + sin θ ₁ × (θ ₂ - θ ₂ ³ / 3!)

As described above, sin θ ₁ and cos θ ₁ are corrected by θ ₂ obtained from the accumulated processing value M2, the overflow set value M2 _max , and the overflow value M _o using the waveform data output from the waveform conversion processing unit 40. can be processed.

By performing such a correction process, it is possible to generate an intermediate value of the waveform data preset corresponding to the number M _o of the address data in the waveform conversion processing section 40 from the correction data, thereby improving the phase accuracy and improving the phase accuracy. Bit precision can be increased. Therefore, even if the waveform data of one pattern is not set with high accuracy, it is possible to output waveform data with high phase accuracy at high speed.

In frequency converters equipped with DDS, the dynamic range and distortion characteristics are affected by the bit precision and bit length processed in the logic circuit. can do.

FIG. 6 is a block diagram of a circuit configuration that achieves resolution corresponding to rational fractions using three phase accumulators. In this example, three phase accumulators shown in FIG. and a low-order phase accumulator P3 corresponding to the number of low-order digits other than the number of high-order digits out of the number of digits other than the number of high-order significant digits. Then, the carry-up data C3 output from the lower-side phase accumulator P3 is connected to be input to the middle-side phase accumulator P2, and the carry-up data C2 output from the middle-side phase accumulator P2 is supplied to the upper-side phase accumulator P1. connected to be input. In this case, the upper side phase accumulator P1 performs address conversion processing, and the middle side phase accumulator P2 and the lower side phase accumulator P3 perform accumulation processing.

The low-order phase accumulator P3 compares the accumulated processed value M3 obtained by accumulating the frequency set value M3 _inc with the overflow set value M3 _{max .} Carry-up data C3 is output.

The middle-order phase accumulator P2 compares the accumulated value M2 obtained by accumulating the frequency setting value M2 _inc and the carry-up data C3 with the overflow setting value M2 _max , and the accumulated value M2 is equal to the overflow setting value M2 _max . If it is larger, it outputs rounding data C2,

The high-order phase accumulator P1 compares the accumulated data L obtained by accumulating the frequency setting value M1 _inc and the carry-up data C2 with the overflow value _Mo , and if the accumulated data L is smaller than the overflow value _Mo , the accumulated data L is accumulated. The calculation data L is output as address data, and when the accumulation data L is equal to or greater than the overflow value _Mo , the difference value between the two is output as address data.

The synthesized phase accumulator _Pc obtained by synthesizing the three phase accumulators P1 to _P3 can be handled on the same operating principle as the case shown in FIG. can be expressed by the formula
Mc _inc =M1 _inc ×M2 _max ×M3 _max +M2 _inc ×M3 _max +M3 _inc
Mc _max =M _o ×M2 _max ×M3 _max
Assuming that the output frequency fc of the accumulated data is the reference frequency fs,
fc=1/Tc=1/(Ts×nc)=fs×( _M1inc × _M2max × _M3max + _M2inc × _M3max + _M3inc )/( _Mo × _M2max × _M3max )
By setting M _o =10 ⁿ and M2 _max =10 ^m to fixed values, the rational fraction frequency can be output according to the value of M3 _max in the denominator.

For example, when M _o =10 ³ and M2 _max =10 ⁷ are fixed, the combined overflow set value Mc _max is Mc _max =M3 _max ×10 ¹⁰ from the above equation.
becomes.

Also, the synthetic frequency setting value Mc _inc is Mc _inc =M1 _inc ×10 ⁷ ×M3 _max +M2 _inc ×M3 _max +M3 _inc from the above equation.
becomes. The output frequency fc is fc=fs×(Mc _inc /Mc _max ) from the above formula.
= (fs/10 ¹⁰ ) x (M1 _inc x 10 ⁷ + M2 _inc + M3 _inc /M3 _max )
Thus, the output frequency fc comes to include a frequency component of 1/M3 _max .

For example, by setting M3 _max =7 and changing M3 _inc between 0 and 6, the output frequency fc can be a frequency containing rational fractions from 0/7 to 6/7 according to the above formula. , it is possible to improve the resolution of the reference frequency with high accuracy.

As described above, it is possible to obtain an output frequency with improved resolution of the reference frequency based on one waveform data.

In the DDS, it is necessary to perform phase modulation processing when outputting by changing the phase amount according to the external signal and data. can be processed by adding or subtracting the data to be

FIG. 7 is a block diagram showing the basic configuration of a DDS having a phase modulation processing section. Since each processing unit described in FIG. 1 performs the same processing, the description is omitted. In this example, the input side of the phase modulation processing section 70 is connected to the output side of the accumulation processing section 20 to receive the accumulated processing value, and the output side is connected to the input side of the address conversion processing section 30. Data that has been connected and modulated is output. Phase modulation data MOD corresponding to the amount of change in phase is input to the phase modulation processing unit 70 from the outside.

The phase modulation data MOD is set to a positive (plus) value or a negative (minus) value. Phase modulation processing is performed by adding or subtracting MOD. As a specific processing method, for example, by converting _MOD as signed binary format data into complementary binary format and using it, 2 Arithmetic processing of addition and subtraction can be performed in base form. The modulation processed value Mm to be output is processed into a format having the same number of significant digits as the accumulated processed value M. If the calculation result is a negative value, the overflow set value _Mmax is added to the negative value to output the modulation processing value Mm as a positive value. Therefore, the phase modulation data MOD should be set to values within the following range.
−M _max +1<MOD<M _max −1

In the above-described example, the phase modulation processing unit 70 is connected between the accumulation processing unit 20 and the address conversion processing unit 30, and the accumulation processing value M is processed based on the phase modulation data MOD to obtain the modulation processing value. Mm is output to the address conversion processing section 30, but the phase modulation processing section 70 can also be connected between the address conversion processing section 30 and the waveform conversion processing section 40. FIG. In this case, the accumulated data output from the address conversion processing section 30 is modulated based on the phase modulation data MOD and output to the waveform conversion processing section 40 . Since the phase modulation process is performed on the accumulated data that has undergone the address conversion process, the resolution may be lower than in the above example. be.

FIG. 8 is a block diagram showing the circuit configuration of the phase modulation processing section 70. As shown in FIG. The phase modulation processing section 70 includes adders 70a and 70b, a subtractor 70c, a sign detector 70d, switches 70e and 70f, an overflow/underflow detector 70g and a latch circuit (FF) 70h.

The adder 70a has an input terminal 70k to which the accumulated value M output from the accumulation processing section 20 is input, an input terminal 70j to which the carry-up data CM output from another phase modulation processing section is input, and a phase modulation It is connected to the input terminal 70m to which the data MOD is input, and outputs the addition value (M+MOD+CM) obtained by adding the phase modulation data MOD and the carry-over data CM to the accumulation processing value M. Since the phase modulation data MOD and the carry-over data CM are data with a positive or negative value and with a sign, the data output from the adder 70a is also data with a sign.

The adder 70b is connected to an input terminal 70n to which the overflow set value M _max is input by the setting section, and adds the overflow set value M _max to the added value (M+MOD+CM) input from the adder 70a ( M+MOD+CM+M _max ) to switch 70e and overflow and underflow detector 70g.

The subtractor 70c is connected to an input terminal _70n to which the set overflow value M _max is input from the setting unit, and obtains a subtraction value ( M+MOD+CM-M _max ) to switch 70e and overflow and underflow detector 70g.

The sign detector 70d detects the sign of the data output from the adder 70a and outputs it to the switch 70e and the overflow/underflow detector 70g.

The switch 70e switches the output from either the adder 70b or the subtractor 70c based on the detection signal from the code detector 70d and performs switching processing to input the output to the switch 70f.

Based on the detection signal from the overflow/underflow detector 70g, the switch 70f selects the added value (M+MOD+CM) output from the adder 70a, the added value of the adder 70b output from the switch 70e, or the subtractor 70c. A switching process is performed so that either one of the subtracted values of is input to the latch circuit 70h.

The overflow and underflow detector _70g detects when the added value (M+MOD+CM) output from the adder 70a is a positive value based on the detection signal from the sign detector 70d, and when the added value is smaller than the overflow set value Mmax. Alternatively, it outputs a detection signal indicating whether it is equal to or greater than the overflow set value _Mmax to the switch 70f.

Then, when the added value is equal to or greater than the overflow set value Mmax, +1 is output to the other phase modulation processing units as carry-up data CM from the output terminal _70q , and the added value is smaller than the overflow set value _Mmax . In this case, 0 is output as carry-up data CM.

A detection signal indicating whether the addition value (M+MOD+CM) output from the adder 70a is a negative value, the addition value is smaller than the overflow setting value _Mmax , or the addition value is equal to or greater than the overflow setting value _Mmax . is output to the switch 70f. Then, if the added value is negative, -1 is output from the output terminal 70q as the carry-up data CM to the other phase modulation processors.

The latch circuit 70h is connected to the input terminal 70i to which the clock signal CL is input, and converts the addition value or the subtraction value output from the switch 70f into the modulation processing value Mm at the input timing of the input clock signal CL. output as The output modulation processing value Mm is output to the outside from the output terminal 70p.

As described above, processing is performed separately for the following three states of the added value of the adder 70a.
(1) When the added value is positive and smaller than the overflow set value _Mmax (2) When the added value is positive and equal to or greater than the overflow set value _Mmax (3) When the added value is negative (additional value is smaller than the overflow set value _Mmax )

In the state (1), the output of the adder 70a is input to the latch circuit FF through the switch 70f and output from the output terminal 70p. In the state (2), the output of the subtractor 70c is input to the latch circuit FF through the switches 70e and 70f and output from the output terminal 70p. In the state (3), the output of the adder 70b is input to the latch circuit FF through the switches 70e and 70f and output from the output terminal 70p.

FIG. 9 is a block diagram relating to an example in which a phase modulation processing section is connected to the DDS shown in FIG. In this example, a phase modulation processing section 70 is connected between the upper side phase accumulator P1 and the waveform conversion processing section 40 to perform phase modulation processing. A latch circuit FF is connected between the middle-order phase accumulator P2 and the correction data conversion processing unit 60 so that data is input to the correction data conversion processing unit 60 in accordance with the timing of the processing of the phase modulation processing unit 70. It has become.

FIG. 10 is a block diagram of an example in which a phase modulation processor is connected to the DDS shown in FIG. In this example, on the output side of each of the upper phase accumulator P1, middle phase accumulator P2 and lower phase accumulator P3, upper phase modulation processing section P1 _mod , middle phase modulation processing section P2 _mod and lower side phase accumulator P1 mod are connected. A phase modulation processor P3 _mod is connected. Then, the round-up data CM output from the lower-order phase modulation processing unit P3 _mod is connected to be input to the middle-order phase modulation processing unit P2 _mod , and the round-up data CM output from the middle-order phase modulation processing unit P2 _mod is connected. Data CM is connected so as to be input to the higher-order phase modulation processing section P1 _mod .

In the above example, since the output of each phase accumulator is modulated by each corresponding phase modulation processing unit and the processing result is reflected in the carry-up data, the phase modulation corresponding to the DDS processing shown in FIG. can be processed.

If the phase resolution/precision required for the phase modulation processing section is not high, the middle-side phase modulation processing section P2 _mod and the low-order phase modulation processing section P3 _mod can be omitted for simplification. For example, when the waveform conversion processing unit has 1,000 pieces of data and is composed only of the upper side phase modulation processing unit P1 _mod ,
A phase modulator with a phase resolution/accuracy of 360 degrees/1,000=0.36 degrees can be obtained, making it possible to produce a phase shift with a phase resolution of 0.36 degrees.

Reference numerals 10: setting processing unit, 20: accumulation processing unit, 30: address conversion processing unit, 40: waveform conversion processing unit (LUT), 50: digital/analog conversion processing unit (DAC ), 60... correction data conversion processing unit, 70... phase modulation processing unit

Claims (7)

A waveform conversion processing unit storing one cycle of waveform data corresponding to a predetermined number M _o of address data, and performing overflow processing using an overflow set value based on an accumulated processing value obtained by accumulating frequency set values. an accumulation processing unit; and an address conversion processing unit for outputting the address data based on the accumulated data obtained from the accumulation processing values for the number of significant significant digits of the overflow set value corresponding to the number of digits of _Mo. A direct digital synthesizer, wherein the waveform conversion processing section outputs the waveform data corresponding to the address data output from the address conversion processing section. The accumulation processing unit is configured to perform overflow processing based on an overflow setting value M _max , and the address conversion processing unit divides the accumulation processing value by (M _max /M _o ) to obtain the accumulated data 2. A direct digital synthesizer as claimed in claim 1, adapted to obtain: The address conversion processing unit includes a high-order phase accumulator corresponding to the number of high-order significant digits, and the accumulation processing unit includes a low-order phase accumulator corresponding to the number of digits other than the number of high-order significant digits. and
The lower-side phase accumulator compares a lower-side accumulated process value obtained by accumulating the lower-side frequency set value with a lower-side overflow set value, which is the overflow set value, and compares the lower-side accumulated process value to the lower-side overflow set value. If it is equal to or greater than
The high-order phase accumulator compares accumulated data obtained by accumulating the high-order frequency set value and the low-order carry-up data with an overflow value M _o and, if the accumulated data is smaller than the overflow value M _o , accumulates data. 2. The direct digital synthesizer according to claim 1, wherein the address data is the sum data, and when the sum data is equal to or greater than the overflow value _Mo , the difference value between the two is output as the address data. The accumulation processing unit outputs correction data for the waveform data based on the lower-side accumulation processing value when the lower-side accumulation processing value in the lower-side phase accumulator is smaller than a lower-side overflow setting value. 4. The direct digital synthesizer of claim 3. The address conversion processing unit includes a high-order phase accumulator corresponding to the number of high-order significant digits. a side phase accumulator and a low-order phase accumulator corresponding to the number of low-order digits other than the number of high-order digits out of the number of digits other than the number of high-order significant digits,
The lower-side phase accumulator compares a lower-side accumulated process value obtained by accumulating the lower-side frequency set value with a lower-side overflow set value among the overflow set values, and the lower-side accumulated process value is set to a lower-side overflow setting. If it is equal to or greater than the value, it outputs the lower side carried data,
The middle-order phase accumulator compares a middle-order accumulation processing value obtained by accumulating the middle-order frequency set value and the lower-order carry-up data with a middle-order overflow set value among the overflow set values, and If the higher-order accumulation process value is equal to or greater than the middle-order overflow set value, the middle-order carry-up data is output,
The high-order phase accumulator compares accumulated data obtained by accumulating the high-order frequency set value and the middle-order carry-up data with an overflow value Mo, and if the accumulated data is smaller than the _overflow value _Mo , 2. A direct digital synthesizer according to claim 1, wherein the accumulated data is output as said address data, and when the accumulated data is equal to or greater than the overflow value _Mo , the difference value between the two is output as said address data. 6. The direct digital synthesizer according to any one of claims 1 to 5, further comprising a phase modulation processing section that changes the phase amount of output waveform data. 6. A phase accumulator used in a direct digital synthesizer according to any one of claims 3 to 5, wherein a predetermined frequency setting value and an accumulated processed value obtained by accumulating carry-up data input from another phase accumulator are When the accumulated value is compared with the overflow set value and is equal to or greater than the overflow value, the difference value between the two is output and new carry-up data is output, and the accumulated value is smaller than the overflow value. A phase accumulator that outputs the accumulated value, if any.

Images