JPH0334312U - - Google Patents
Info
- Publication number
- JPH0334312U JPH0334312U JP9411789U JP9411789U JPH0334312U JP H0334312 U JPH0334312 U JP H0334312U JP 9411789 U JP9411789 U JP 9411789U JP 9411789 U JP9411789 U JP 9411789U JP H0334312 U JPH0334312 U JP H0334312U
- Authority
- JP
- Japan
- Prior art keywords
- data
- digit
- frequency
- waveform data
- setting means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013500 data storage Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は一実施例の動作を説明するためのタイミ
ング図、第３図は一実施例の動作を説明するため
のメモリ図である。第４図は本考案の他の実施例
を説明するための要部回路図、第５図および第６
図は本考案の他の実施例を示す要部ブロツク図で
ある。第７図はデジタルシンセサイザの基本構成
を示すブロツク図、第８図は従来装置を示すブロ
ツク図である。
１０……周波数設定部、１１……上位シフトレ
ジスタ、１２……上位設定レジスタ、１４……Ｂ
ＣＤ加算器、１５……キヤリレジスタ、１７……
下位シフトレジスタ、１８……下位設定レジスタ
、２０……上位加算器、２２……下位加算器、２
４……ＲＯＭ回路、２５……ＤＡ変換器、２６…
…分周器。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a timing diagram for explaining the operation of one embodiment, and FIG. 3 is a memory diagram for explaining the operation of one embodiment. FIG. 4 is a main circuit diagram for explaining another embodiment of the present invention, and FIGS.
The figure is a main part block diagram showing another embodiment of the present invention. FIG. 7 is a block diagram showing the basic configuration of a digital synthesizer, and FIG. 8 is a block diagram showing a conventional device. 10...Frequency setting section, 11...Upper shift register, 12...Upper setting register, 14...B
CD adder, 15...Carry register, 17...
Lower shift register, 18... Lower setting register, 20... Upper adder, 22... Lower adder, 2
4...ROM circuit, 25...DA converter, 26...
...divider.
Claims (1)
倍にして設定する周波数設定手段１０と、 前記周波数設定手段に設定されたデータに応じ
たステツプで変化するアドレス値を出力するアド
レス可変手段２０〜２３と、 予め所定の波形データが記憶され、前記アドレ
ス値に対応する波形データを出力する波形データ
記憶手段２４と、 前記波形データ記憶手段から順次出力される波
形データをアナログ信号に変換して出力するデジ
タルアナログ変換器２５と、 前記アナログ信号を１／Ｎに分周する分周器２
６とを備えたデジタルシンセサイザにおいて、 前記周波数設定手段は、前記複数桁のＢＣＤコ
ードの周波数データを、下位の桁から順に１桁ず
つ受け、該受けた１桁のデータと前桁のキヤリデ
ータとを加算し、Ｎ倍して得られたデータを、下
位の桁から順に設定するように構成されているこ
とを特徴とするデジタルシンセサイザ。[Claims for Utility Model Registration] N
A frequency setting means 10 for setting the frequency by double; address variable means 20 to 23 for outputting an address value that changes in steps according to the data set in the frequency setting means; predetermined waveform data is stored in advance; a waveform data storage means 24 that outputs waveform data corresponding to an address value; a digital-to-analog converter 25 that converts the waveform data sequentially output from the waveform data storage means into an analog signal and outputs the analog signal; /N frequency divider 2
6, the frequency setting means receives the frequency data of the multi-digit BCD code one digit at a time starting from the lowest digit, and combines the received one-digit data with the carrier data of the previous digit. A digital synthesizer characterized in that the digital synthesizer is configured to add data obtained by adding up and multiplying by N, and to set the data in order from the lowest digit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9411789U JP2561394Y2 (en) | 1989-08-10 | 1989-08-10 | Digital synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9411789U JP2561394Y2 (en) | 1989-08-10 | 1989-08-10 | Digital synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0334312U true JPH0334312U (en) | 1991-04-04 |
| JP2561394Y2 JP2561394Y2 (en) | 1998-01-28 |
Family
ID=31643458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9411789U Expired - Lifetime JP2561394Y2 (en) | 1989-08-10 | 1989-08-10 | Digital synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2561394Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0754179A (en) * | 1993-08-06 | 1995-02-28 | Kimura Chem Plants Co Ltd | Washing and drying device |
| JP2022159932A (en) * | 2021-04-05 | 2022-10-18 | 興治郎 川井 | direct digital synthesizer |
-
1989
- 1989-08-10 JP JP9411789U patent/JP2561394Y2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0754179A (en) * | 1993-08-06 | 1995-02-28 | Kimura Chem Plants Co Ltd | Washing and drying device |
| JP2022159932A (en) * | 2021-04-05 | 2022-10-18 | 興治郎 川井 | direct digital synthesizer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2561394Y2 (en) | 1998-01-28 |
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