JPH04212516A - Signal generation circuit - Google Patents

Abstract

PURPOSE:To respectively arbitrarily set the pulse intervals, pulse widths and pulse amplitudes of respective pulse signals with small scale circuit configuration. CONSTITUTION:A pulse interval storage part 2, pulse width storage part 3 and pulse amplitude storage part 4 are provided to store respective pulse intervals, pulse widths and pulse amplitudes and by a pulse interval detection part to output a pulse interval detection signal (e) while receiving a reference clock (d) from a reference clock generation part 1, pulse width comparator 10 to output a pulse width detection signal (g), and digital/analog conversion part 5 to convert the output data of the pulse amplitude storage part 4 to an analog voltage, the pulse signals having the respectively arbitrary pulse intervals, pulse widths and pulse amplitudes are generated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generating circuit, and more particularly to a signal generating circuit capable of arbitrarily setting and outputting each pulse interval, pulse width, and pulse amplitude.

0002

[Prior Art] A conventional signal generation circuit has a certain time interval Δ
An amplitude storage unit that stores an arbitrary amplitude value every t, a readout unit that sequentially reads out the amplitude values stored in the amplitude storage unit, and a continuous voltage that reads the amplitude value every Δt read by the readout unit. The voltage conversion unit converts the voltage into a waveform.

[0003] In addition, conventionally, a pulse signal generating circuit that outputs only a pulse-like waveform has a pattern storage section that sets and stores the output signal as a code pattern using 0s and 1s, and a The device was configured to include a readout unit that sequentially reads out patterns, and was able to obtain a pulse signal output of a desired pattern with a constant amplitude.

0004

[Problems to be Solved by the Invention] The conventional signal generating circuit described above is configured to set and store the amplitude value for each Δt over the entire length T of the desired waveform.
When T is longer than that, an enormous storage circuit and a complicated readout circuit are required, and it also takes a lot of time to set the amplitude value. Further, the conventional pulse signal generation circuit outputs only pulse signals with constant amplitude, and therefore has the disadvantage that it is not possible to obtain pulse signals with various amplitude values in a series of pulse trains.

[0005]

[Means for Solving the Problems] A signal generation circuit of the present invention includes a reference clock generation section, a pulse interval storage section that stores a pulse interval for each pulse, and a signal generation circuit that receives an output reference clock from the reference clock generation section. a pulse interval detection section that detects that the pulse interval time reaches the output data value of the pulse interval storage section; a pulse width storage section that stores the pulse width of each pulse; and a pulse width storage section that receives the reference clock and detects the pulse width time. a pulse width detection unit that detects that the pulse width has reached the output data value of the pulse width storage unit; a pulse amplitude storage unit that stores the pulse amplitude of each pulse; and a pulse width detection unit that stores the pulse amplitude of each pulse; It is configured to include a digital-to-analog converter for conversion.

[0006]

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

The signal generating circuit shown in FIG. and a data setting section 11 that sets data in each of the pulse amplitude storage section 4 and the pulse interval storage section 4, a pulse interval counter 7 that counts the output clock of the reference clock generation section 1, and a count value of the pulse interval counter 7 and the pulse interval storage section 2. The pulse interval comparator 8 detects that the data are equal, the pulse width counter 9 counts the output clock of the reference clock generation section 1, and the count value of the pulse width counter 9 and the data in the pulse width storage section 3 become equal. a pulse width comparator 10 that detects a pulse width comparator 10, a pulse counter 6 that receives a detection signal from the pulse interval comparator 8 and counts the number of pulses, and a digital-to-analog converter 5 that converts the output data of the pulse amplitude storage section 4 into an analog voltage value. , a switching unit 13 that switches between the output voltage value of the digital-to-analog converter 5 and the ground, and a pulse counter 6
A flip-flop 1 is set when the count value changes and is reset by the detection signal of the pulse width comparator 10.
4.

The operation will be explained step by step using the output signal waveform diagram in FIG. The data setting unit 11 activates the selection signal a to the selection unit 12, makes the address signal b of each storage part control effective, passes the data signal c, and sets the pulse interval Ti to the pulse interval storage part 2, and sets the pulse interval Ti to the pulse width storage part. 3 and the pulse amplitude Pi in the pulse amplitude storage section 4, respectively. When all data is set and the signal output state is reached, the selection signal a becomes inactive and the address signal b is controlled by the output value of the pulse counter 6.

The pulse interval counter 7 counts the number of clocks of the reference clock d, which is the output signal of the reference clock generator 1, and outputs the count value to the pulse interval comparator 8. The pulse interval comparator 8 compares the count value of the pulse interval counter 7 with the data at the address in the pulse interval storage section 2 specified by the address signal b, and when the two match, outputs the pulse interval detection signal e to the pulse counter. 6, a clear signal f is output to the pulse interval counter 7. Therefore, the count value of the pulse interval 6 increases by 1, and the address signal b specifies the next address, and at the same time, the pulse interval counter 7 returns to its initial state and becomes ready to measure the next pulse interval.

The pulse width counter 9 counts the number of reference clocks d when the pulse width signal h, which is the output signal of the flip-flop 14, is active, and outputs the count value to the pulse width comparator 10. The pulse width comparator 10 compares the count value of the pulse width counter 9 with the data at the address in the pulse width storage unit 3 specified by the address signal b, and when the two match, sends the pulse width detection signal g to the flip-flop 14. Output to the reset terminal of.

In the flip-flop 14, a count change signal j outputted when the count value of the pulse counter 6 changes is connected to a set terminal, and an output pulse width detection signal g of the pulse width comparator 10 is connected to a reset terminal. Therefore, the output pulse width signal h is in an active state for a period corresponding to the output data value of the pulse width storage section 3 from the rising edge of the pulse, and thereafter becomes an inactive state. On the other hand, the data at the address in the pulse amplitude storage section 4 designated by the address signal b is converted into an analog voltage by the digital-to-analog conversion section 5 and input to one input terminal of the switching section 13 . The other input terminal of the switching section 13 is connected to ground.

The switching control signal of the switching unit 13 is a pulse width signal h which is the output of the flip-flop 14.
The output terminal of No. 3 is connected so that when the pulse width signal h is active, the output voltage of the digital-to-analog converter is output, and when it is inactive, the ground side is output. Therefore, when the pulse width signal h is active, the output terminal 20 outputs the signal to the pulse width storage section 4 only when the pulse width signal h is active, that is, only for the set time width of the pulse width storage section 3.
The set amplitude pulse becomes the output signal, the pulse interval becomes the value set in the pulse interval storage section 2, and the output signal waveform as shown in FIG. 2 is obtained.

FIG. 3 is a block diagram showing a second embodiment of the present invention. The output clock of the reference clock generation section 1 is converted into a pulse interval count frequency division ratio signal q from the data setting section 11.
A pulse interval count frequency dividing circuit 22 that divides the frequency according to the pulse interval counter 7 is located immediately before the clock input section of the pulse interval counter 7, and also divides the output clock of the reference clock generation section 1 into the data setting section 1.
The pulse width counter 9 is a pulse width count divider circuit 23 that divides the frequency according to the pulse width count division ratio signal r from 1.
It is located just before the clock input section.

For example, if the pulse interval count frequency division ratio signal q is 1/2, the pulse interval count frequency division circuit 22 inputs one pulse per pulse of the reference clock d to the clock input section of the pulse interval counter 7. Figure 2
The pulse interval Ti is uniformly doubled. Similarly, the pulse width ti can be uniformly changed by the pulse width count divider circuit 23. Therefore, these two frequency divider circuits, the pulse interval count frequency divider circuit 22 and the pulse width count frequency divider circuit 23, make it possible to uniformly change the pulse interval and pulse width of the output signal.

[0015]

[Effects of the Invention] The signal generation circuit of the present invention is capable of setting each pulse individually by providing a pulse interval storage section, a pulse width storage section, and a pulse amplitude storage section. This has the advantage that an arbitrary pulse signal waveform with variable amplitude can be obtained with a small-capacity storage circuit and a small-scale circuit configuration. Furthermore, the signal waveform can be set in a relatively short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram showing an output signal obtained by the present invention.

FIG. 3 is a block diagram showing a second embodiment of the invention.

[Explanation of symbols]

1. Reference clock generation section 2 Pulse interval memory section 3 Pulse width storage section 4 Pulse amplitude storage section 5 Digital-analog conversion section 6 Pulse counter 7 Pulse interval counter 8 Pulse interval comparator 9 Pulse width counter 10 Pulse width comparator 11 Data setting section 12 Selection section 13 Switching section 14 Flip-flop

Claims (1)

[Claims] 1. A reference clock generation section, a pulse interval storage section that stores the pulse interval for each pulse, and output data of the pulse interval storage section that receives the output reference clock of the reference clock generation section and determines the pulse interval time. a pulse interval detection section that detects that the pulse width has reached the value; a pulse width storage section that stores the pulse width of each pulse; and a pulse width storage section that receives the reference clock and detects when the pulse width time reaches the output data value of the pulse width storage section. a pulse width detection section for detecting the pulse width, a pulse amplitude storage section for storing the pulse amplitude of each pulse, and a digital-to-analog conversion section for converting the output data of the pulse amplitude storage section into an analog voltage. Characteristic signal generation circuit.