SU1343541A1 - Digital three-phase oscillator - Google Patents

Description

The invention relates to radio engineering and communications, measuring equipment and can be used in tests and studies of various systems, as well as for calibration and adjustment of measuring instruments and stands.

The purpose of the invention is to reduce the nonlinear distortion of the output signals.

The drawing shows a structural electrical circuit of a digital three-phase generator.

The digital three-phase generator contains a reference generator 1, a frequency divider 2, the first counter 3 is a permanent memory unit 4, a phase code set unit 5, a second counter 6, a digital-to-digital converter 7, a third counter 8, a first multiplexer 9, a sampling-storage unit 10, the decoder 11, the amplitude code setting unit 12, the code divider 13, the phase shift generating unit 14, the second multiplexer 15.

Digital three-phase generator works as follows. The sequence of clock pulses from the output of the reference generator 1 through the divider 2 frequency is fed to the first counter 3, the conversion factor is six. The pulses from the third bit output of the first counter 3 are fed to the counting inputs of the second 6 and third 8 counters, each time changing their state by one. S5p The March conversion factor of counters 6 and 8 is equal to the number of sampling levels of the output sinusoidal signal per period.

At the outputs of the first multiplexer 9, in the first three cycles, the code values from the bit outputs of counter 8 are set, and in the next three cycles, the code values from the bit outputs of counter 6 are set. These code values are set in the first and fourth cycles, respectively, on the outputs of the second IS multiplexer whose operation is controlled by the first and second bit outputs of the counter 3.

In the second, fifth, third, and sixth cycles, the code value at the outputs of the second multiplexer 15 is determined by the generation unit 14, resulting in no. the outputs of the second multiplexer 15 are the codes of the addresses of the phases, which are fed to the input of the block 4 of constant memory), and the codes of the marks, which are fed to the input of the digital-analogue converter 7.

Codes from the outputs of block 4 of permanent storage are received at the information inputs of the divider 13 codes controlled by block 12 of the amplitude code setting. Setting the required amplitude of the output signals is performed by controlling the installation unit 12 and the decoder 11, as a result of which the values obtained at the outputs of the divider 13 of the codes are converted using the digital-analogue converter 7 and the sampling-storage unit 10 in the output voltage.

Claims (1)

Invention Formula A digital three-phase generator containing a series-connected reference generator, a frequency divider, the first counter, the first, second and third bit outputs of which are connected to the corresponding inputs of the decryptor, are connected in series to an amplitude code setting block, the input of which is connected to the output of the distributor, the code divider, the digital-to-analog converter and the sample-storage unit, the phase code setting unit, the second counter and the first multiplexer, and the third counter, the output of the higher bit which is connected to the input setting the initial state of the second counter, and the outputs of the other bits - with the corresponding inputs of the first multiplexer, the block of permanent storage, the output of which is connected to the information input of the code divider, while the third bit output of the first counter is connected to the counting inputs of the second and third counters and the control input of the first multiplexer, the output of the decoder is connected the control input of the sample-storage unit, characterized in that, in order to reduce the non-linear distortion of the output signals, sequentially connected forming unit is introduced phase shifts and the second multiplexer, the first output of which is connected to the sign input of the digital-to-analog converter, and the second output - to the address input of the constant-313A35A14 block memory, the bit input of the block of the block is connected respectively to the first world phase shifts and the second infor and second bit outputs of the first the math input of the second multiplexer, and the control input connected to the bit output of the first unit for the formation of phase shifts of the multiplexer connection, and the first and second 5 second bits of the output, the top address inputs of the second multiplex counter.