SU1241518A1 - Device for generating signal with multiple differential phase shift modulation - Google Patents

Abstract

The invention relates to telecommunications. Improving formation accuracy. The device contains separator 1 of the information sequence, in short, transcoder 2, unit 3 for introducing relativity, shaper 4 clock sequences, memory cells 5, main switches 6 carrier oscillations (NK), amplitude shaper (AF) 8 NK source 9, filter 11 low frequencies, counter 12, a persistent storage device 13, D / A converter 14, the Goal is achieved by introducing delay (EZ) 10 elec tors and additional switches NK 7. EZ 10 allows to obtain a set of NK rectangular shapes, each of which delayed relatively sponding to the original oscillation angle. P / 6. Switches 7 provide simultaneous connection to the AF 8 input of the delayed and initial NC. These oscillations are summed up in AF 8, at the output of which a signal is formed that does not contain 3rd-harmonic modulation products in its spectrum, which ensures high accuracy of output signal formation. 2 Il. (L C -4 I g el 00

Description

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Image mesh refers to telecommunications and can be used in discrete information transmission systems.

The purpose of the Invention is to improve the shaping accuracy.

Fig. I is a structural electrical circuit diagram of the device; Fig. 2 illustrates stress plots showing its operation.

The device contains separator 1 of information sequence by krams, transcoder 2, unit 3 for input of relativity, shaper 4 clock sequences, memory cells 5, main switches 6 of carrier oscillations, additional switches 7 of carrier oscillations, amplitude driver 8, source 9 of carrier oscillations, elements 10 is a delay and a low-pass filter 11, with the amplitude driver 8 comprising a counter 12, a persistent storage device 13, and a digital-to-analog converter 14.

The device works as follows. .

The delay elements 10 allow to obtain a set of rectangular-shaped oscillation carriers, each of which is delayed relative to the corresponding initial oscillation.

angle

Jt

-. When adding two

rectangular signals delayed relative to each other; by 2, a signal is obtained, the form of which is shown in fig. The Fourier series decomposition of a function of this kind is represented as follows:

,

T - (cosoC sin X + + g cos ZrC sin 3 X + g cos 5о С sin 5х + .. „.).

When about {g the expression cos 3, about sin 3x oJ.

turns into O, since it corresponds to the third harmonic, it is absent in the sum signal.

 Additional switches 7 provide simultaneous switching1241518

to the input of the amplitude shaper 8 of the delayed and initial carrier oscillations. These oscillations are summed up in an amplitude driver 8, at the output of which a signal is generated.

not containing in its spectrum

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third harmonic modulation products. .

In the absence of the output of the amplitude shaper 8, the frequency components of the third-harmonic modulation products, the task of separating the modulation products of higher harmonics (5.7, etc.) from the spectral components of the useful signal is solved by using a low-pass filter 11.

The separator 1 of the moles information sequence is a shift register and is intended to convert the information pulse sequences into a parallel code whose width is equal to the modulation ratio.

Nerecoder 2 is designed to convert the p-bit data code, in accordance with the modulation code, into a binary number, which determines the phase shift of the carrier oscillation of the next single signal relative to that of the previous oscillation of the previous single signal.

Relativity input unit 3 is made in the form of an accumulating adder, the output binary code of which determines the phase of the carrier oscillation of the current single signal.

At the moments of modulation, a binary number from the output of the transcoder 2 is applied to the input of the adder, which determines the phase shift of the next single signal.

When C, the number received from the output of the transcoder 2 with the number stored in the accumulator, we get a new number that determines the value of the phase of the carrier oscillation of the next single signal. In this case, the phase of the next single signal changes relative to the phase of the previous signal by an amount determined by its K) type of parallel binary information code.

The 4 clock sequence shaper is designed to generate control and timing signals for the device nodes and is a frequency divider.

31241518

The memory cells 5 are designed to store the results of the summation generated by the relativity input unit 3 for M clock intervals. 5

The main and additional switches 6 and 7 are designed to switch carrier oscillations with different phases in accordance with the control signals coming from the memory 5 of the cells 5 and are multiplexers.

Amplitude driver 8 is designed to sum up rectangular-shaped carrier oscillations that follow each other with a delay P

r and multiplying this sum by the signal envelope of the information sequences.

A sequence of information pulses from an information source is fed to one input of the separator 1, and to the other input, a clock frequency from the output of the 4 clock sequences generator. Separator 1 converts the information sequence into a parallel n-bit code of the data arriving at the input of the transcoder 2.

The decoder 2 converts the n-bit data code in accordance with the molding code into a binary number, which determines the phase shift of the carrier oscillation of the next unit signal relative to the phase of the carrier line of the previous unit signal.

Then the recoded data is delivered to the input of the input unit 3, for the synchronizing course of which the clock frequency arrives. The binary number from the output of the decoder 2 is summed with the number that is wounded in the input ratio block 3 and at its output a number is formed that determines the value of the basics of the carrier oscillation of the next output signal. Each new cumulative result is alternately written to one of 5 memory locations, and stored there for M clock slots.

The output signals of memory cells 5 govern the operation of ocHoBiftix and additional switches 6 and 7.

The inputs of the main and additional switches 6 and 7 are not 20

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the device is up to the input

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actual frequencies formed by a source of 9 carrier waves.

The carrier frequencies of the source 9 carrier waves are generated from square-wave signals produced by the 4 clock sequence generator. In this case, the frequency of the carrier oscillation is 1.8 kHz at one input of the source 9 of the carrier oscillations, and the frequency determining the shift of the information is transmitted at the other input. signals in the source of 9 unperturbed oscillations, which is equal to 1, 2 k-Hz, where n is the modulation ratio. Such a choice of the frequency of the shift ensures the formation on the output of the source 9 of carrier oscillations of a set of frequencies, the phase shift between which

rymi is a multiple of t-. 2n

These carrier frequencies are fed to the inputs of the main switches 6 directly (figure 2, a), and to the inputs of additional switches. 7 - delayed by elements of 10 delays on.

angle - (2, 5).

The signal from the outputs of the main and additional switches 6 and 7 is fed to the address inputs of the persistent storage device 13 of the amplitude driver 8. At the same time, the other address inputs of the permanent storage device 1 3 receive a binary number from the output of the counter 12, which is generated by counting the input signal pulses and corresponds to discrete values of the envelope of the formed signal.

The set of signals arriving at the address inputs of the persistent storage device 13 sets the readout address of the sampled values of the output signal. The values of these samples are the result of evaluating the following expression:

(a + a /) b2- + (a j, + a.) b + + + () bz.

- where a, ..., and IV, are the values of the carrier oscillations of rectangular shape, formed by the source 9 of the carrier oscillations;

aj (,,. ,, ats-values of the same oscillations, detained by elements 10

delay at aa angle

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3

g.

Bfvj sample values

the envelope of the information parcel for each given point in time determined by the state Z of the counter 12 and the parcel number from 1 to M

At the output of the permanent storage device 13, a sample of the current values of the phase-modulated signal, represented in binary code, is formed. This signal is then fed to the input of the diffraction threshold converter 14, at the output of which an analog phase-dated signal is formed. This signal is fed to a low-pass filter 1, which suppresses the parasitic modulation products of 5.7.9 and higher harmonics. The output of the filter is 11 ncs, 1 1 is the output of a signal shaping device with multiple relative phase modulation.

Thus, the proposed device generates a signal with multiple relative phase modulation, the spectrum of which does not contain third-harmonic modulation products, which ensures a high accuracy of output signal formation.

Claims (1)

Invention Formula A device for generating a signal. With multiple relative phase modulation, comprising a serially connected separator of the information sequence in multiples, a transcoder and a block. relativity, the outputs of which are connected to the inputs of memory cells, the outputs of which are connected to the first inputs of the respective main carrier-carrying switches, the outputs of which are connected to the first address inputs of the amplitude driver, the output of which is connected to the input of the low-pass filter, the second inputs of the main switches of the carrier oscillations are connected to the outputs of the source of carrier oscillations, the inputs of which, as well as the synchronizing inputs of the separator of the information sequence, the input of relativity, amplitude driver and memory cells are connected to the corresponding clock sequence generator outputs, characterized in that, in order to improve the formation accuracy, delay elements and additional load switches, their oscillations are introduced, while the outputs of the carrier wave source are connected to the information inputs of the delay elements, the outputs of which are connected to the first inputs of the corresponding additional switches carrier oscillations, the second inputs of which are connected to the outputs of the corresponding beams of the fifth am, the outputs of the additional commutators of carrier oscillations cheny second address inputs to an amplitude shaper and the further output of the clock timing sequence connected to the inputs of delay elements. Y a I P 7G / 3 Lllll 0 JC 2Jr 3Jr ff Sir e lit 0ae. g