SU1197102A2 - Autocorrelation meter of parameters of pseudorandom phase=shift keyed signal - Google Patents

Abstract

1. AUTO-CORRELATION MEASURE OF THE RIELER OF THE PARAMETERS OF A Pseudo-Accidental Phase-Manipulation Signal on the author. St. No. 708521, I differ from the fact that, in order to expand the functionality by ensuring the definition of the structure of the received pseudo-random sequence, sequentially connected pulse generator and recurrent processing unit are entered into it, while the information input of the recurrent processing unit is connected to the output of the key, and the pulse driver input is connected to the output of the first low-pass filter. / "P-4/5

Description

, i 1

2. The meter according to claim 1, characterized in that the recurrent processing unit contains an additional pulse generator, connected in series with the first shift register, whose recording input is. is the information input of the recurrent processing unit., the element ILINE, the inverter and the first element AND, whose second input is the clock input of the recurrent processing unit serially connected second additional multiplication unit, modulo two, the second element AND, the element OR, the second the shift register and the third shift register, the outputs of the bits of which are the outputs of the recurrent processing unit, and the series-connected clock generator, the counter and the additional delay element, while

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the output of the first element AND is connected to the initial input of the first shift register, whose corresponding diodes are connected to the corresponding inputs of the second additional multiplication unit, the output of the OR element is NOT connected to the second input of the second element AND, to the input of the clock generator, and to the input of the additional pulse shaper, the output of which is connected to the second input of the OR element, the output of the additional delay element is connected to the synchronous input of the third shift register and to the inputs of the installation of the counter of the first and second shift registers, and the output of the clock pulse generator is connected to the synchronous input of the second shift register, the corresponding outputs of which are connected to the corresponding inputs of the second additional multiplying unit.

H: .- The invention is RELATED to telecommunications and can be used as a device for processing phase-shifted (FM) signals in discrete information transmission systems, in combined radar communication systems, where pseudorandom FM signals with J / J shift are widely used improvement of the known device according to the main ed. St. No. 708521:

The purpose of the invention is to enhance the functionality by providing a definition of the structure of the received pseudo-random sequence.

FIG. 1 shows the structural electrical circuit of the autocorrelation meter of the parameters of the pseudo-slave FM signal in FIG. 2 Structural electrical block diagram of recurrent processing.

The autocorrelation meter of pseudo-random phase-manipulated signal contains a multiplier 1, a delay element 2, a band-pass filter 3, a non-linear element 4, the first low-pass filter 5, a tuning rate generator 6, and the second low-pass filter 7. frequency meters, frequency meters 8 and 9, phase shifter 10, balanced manipulator 11, key 12, additional multiplication unit 13, integrator 14, unit 15 for measuring phase shift values, recurrent processing unit 16 and pulse shaper 17, with recurrent block 16 The processing consists of 0. first register 18 shift element

i OR-NOT 19, the inverter 20, the first and second elements AND 21 and 22, the additional driver 23 pulses, the element OR 24 ,. second register

15 25 shift, generator 26 clock pulses, the counter 27, the second additional block 28 multiplying, the adder 29 modulo 2, an additional element 30-delay and the third register 31 of the shift.

The autocorrelation meter for pseudo-random phase-amplified signal operates as follows.

25 The signal to be processed PSP from the output of the first low-pass filter 5 (LF) through the key 12 is fed to the information input of the recurrent processing unit 16, to the clock

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the input of which, from the output of the driver of 17 pulses, arrives pulses of the clock frequency of the bandwidth bandwidth, formed from sinusoidal oscillations of the clock frequency, provided by the first filter 5 5 rom 5.

The operation of the recurrent processing unit is based on the following mathematic relationships. The structure of any generator of the memory bandwidth can be described as a polynomial tMOM feedback of the form h (x) he ® h., X Ф h2x2 © where X is a discrete variable; h are the coefficients of the polynomial relation; n is the degree of the polynomial, is equal to the non-shift register of the SRP generator. From the algebraic structure of the linear PSP, it follows that the recurrence relation for the internal element at the output of the generator PSP to.,. -... einak.n for and: k N, where N is the length of the generated PSP; cap symbol. And for each subsequent element of the bandwidth can be written, ©. .. “kn h, a (+). . @ B „a. tf n-1 h 9 - in the period of the SRP, there is one and only one series of (n-1) zeros - the zero series of the maximum length. If as the binary symbol a, in the discharge (I), select the first binary of the series (n-1) zero, then the binary symbols KK + 1 and, consequently. K-1 If the values of the selected characters in this way are substituted into (1), we obtain

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About .Vt). ...

About h © hja.G). .. (.

0 h., „.,

1 N hn 1 hn-1, a k-2 hn-z k-3 Chak-2® a.3® .. (; In the recurrent processing unit, all bits of the first register 18 are in the initial state in a single state All bits of the second register 25 are in the zero state, the counter 27 is in the zero state, the clock oscillator generator 26 is turned off. The clock frequency pulses through the open first element 21 and enter the syncro input of the first register 18, and the received the memory bandwidth segment arrives at its information input and is sequentially recorded in the bits of this register. When recording in the first bits of the first register Page 18 of the zero series PSP of maximum length (series of (n-1) zeros) the element OR NOT 19 forms the level of a logical unit at the inverse output, which closes the first element and 2 through the inverter 20 and thus disables the sync input first register 18. Recorded in the first register 18 at this point, the segment of the bandwidth freezes.At the same time, the signal of the logical unit from the output of the element OR NOT 19 opens the second element 22, turns on the generator 26 clock pulses and enters the input of the additional imager 23 pulses at the output of which A pulse with the level of a logical unit and a duration of a greater duration of the clock pulses of the generator 26, the shortest period of the clock pulse of the j-generator 26. This pulse together with the first clock of the generator 26 sets the first bit of the second register 25 together with the first clock of the generator 26 in one state (this corresponds to the value of the coefficient h). In the second additional multiplication unit 28, the value of h is multiplied by the corresponding symbol SRP recorded in (n + 1) bit register 18, and the result obtained (corresponding bn) by the second clock, generator 26 is recorded in the first bit of the second register 25 , and the value of h, 1c is shifted in this way to the second bit. The value of h,.;, y fflozhatc per symbol SRP in the second additional 28 multiplication and the value of hf, is multiplied in it. on the SRP symbol a | recorded in the (n + 2) -th element of the first register 18. The multiplication results are added modulo two in the adder 29, and the result (corresponding to the value of h) by the third clock of the generator 26 is recorded for the first bit of the second register 25 .. The values of h., And hj, are shifted by the same beat to the next bits. After the n cycles, in the second register 25 all the coefficients of the feedback polynomial of the PRS generator will be written: b, h.,. .., hj, h, calculated in accordance with the System of Equations 024 (2). At the same time, with the p-th clock at the output of the counter 27 (modulo p), an overflow pulse is formed, which, after the delay time necessary to set the second register 25 to a steady state, goes to the syncro input of the third register 31 , in the bits of which the parallel code rewrites the values of the coefficients of the polynomial from the bits of the second register 25. The values of the coefficients will be stored in the bits of the register 31 until the next operation of the entire block. At the same time, the overflow pulse of the counter 27 sets the bits of the first and second registers 18 and 25 and the counter 27 to their initial state. At the output of the element RSHI-NOT 19, a logical zero signal appears, which opens the first element I 21 through the inverter 20, and the clock pulses arrive at the counting input of the first register 18. I. Thus, the recurrent processing unit searches for a zero series of maximum length and determines the values of the coefficients of the feedback polynomial generator of the SRP transmitter of the FM signal. And the values of the feedback polynomial coefficients unambiguously determine the structure of the SRP generator.

Claims (2)

1. AUTOCORRELATION MEASURING PARAMETERS PSEUDOUS St. No. 708521, I distinguish with the fact that, in order to expand the functionality by providing a definition of the structure of the received pseudo-random sequence, sequentially connected pulse shaper and a recurrent processing unit are introduced into it, while the information input of the recurring processing unit is connected to the output of the key, and the input of the pulse shaper is connected to the output of the SU, 1197102 2. The meter according to π, 1, characterized in that the recurrence processing unit contains an additional pulse shaper connected in series to the first shift register, the recording input of which is the information input of the recurrence processing unit., ORINE element, inverter and * first element AND, second. input of which is the clock input of the recursive processing unit _sequentially connected second additional multiplier, modulo two adder, a second aND gate, an OR gate, a second shift register and the third register of translations ha, the outputs of the discharges of which are the outputs of the recurrent processing unit, and a series-connected clock generator, a counter and an additional delay element, while the output of the first element And is connected to the input of the first shift register, the corresponding outputs of which are connected to the corresponding inputs of the second additional multiplication unit, the output element OR NOT connected to the second input of the second element — AND, to the input of the clock pulse generator and to the input of the additional pulse shaper, output which is connected to the second input of the OR element, the output of the additional delay element is connected to the clock input of the third shift register and to the input inputs of the counter of the first and second shift registers, and the output of the clock generator is connected to the clock input of the second shift register, the corresponding outputs of which are connected to the corresponding inputs of the second additional multiplication block. 1 ·