SU796834A1 - Pseudorandom pulse train generator - Google Patents

Description

The invention relates to computing and can be used in simulating random processes. A known generator of a pseudo-random sequence of pulses, containing a shift register with a modulo two torus and a delay line in the feedback circuit. This generator is characterized by the maximum possible speed determined by the propagation time of the signal in one bit of the shift register 1. However, this is achieved due to the loss of widebanding (with a decrease in the clock frequency, the period of the sequence decreases). Closest to the invention is a pseudo-random pulse train generator containing a shift register with an absolute modulo two in the feedback circuit f2. The disadvantage of this generator is the low speed determined by the total signal propagation time in one bit of the shift register and modulo two. The purpose of the invention is to increase the speed of the generator without losing bandwidth. To achieve this goal, in a known pseudo-random pulse sequence generator containing a shift register with an absolute modulo two in the feedback circuit, a NOT element, a delay element and an OR — NOT element are inputted, the output of which is connected to the shift register input and NOT connected to its first input, the second input of the element OR is NOT connected to the direct output of the delay element, and the modulo two adder contains three elements OR-NOT, the inputs of the first of which are connected to the direct outputs of the h-th and th-th bits of the registers Shift country, inverse outputs of which are connected to the inputs of the second OR-NOT element, inputs of the third OR-NOT element are connected respectively to the outputs of the first and second OR-NOT elements and to the inverse output of the delay element, whose input is connected to the clock pulse bus. The drawing shows the generator block diagram.

The generator contains a register 1 shift with adder 2 modulo two in the feedback circuit. The first bit of the 1.1 register is performed on the delay element 1.1.1, the fourth OR OR NOT 1.1.3 element and the inverter 1.1.2 is the trigger, and the adder 2 is on the first 2.1, the second 2.2 and the third 2.3 OR-NOT elements.

The generator works as follows.

When applying single clock pulses and the presence in the register 1 of the preliminary non-zero information, the latter begins to shift it. The duration of the clock pulses, in this case, is chosen equal to

() tn6ip

where tj, is the time; spreading: of the signal in the OR-NOT element; tp - delay recording signal

raz de.

. In the pause between clock pulses from the direct input of the 1.1.1 delay element, the zero level is removed, and the synchronous one is zero, therefore the adder 2 is blocked (its output is zero), and the trigger 1.1 is in a steady state. With the arrival of the clock pulse, the adder 2 opens (a signal appears at its output, I corresponds to the sum modulo two signals l.i and l.m bits), and the trigger 1.1 translates to the zero state. Since elements 1.1.3 and 2.1 OR do NOT form a wired OR, the resulting signal at the output of bit 1.1 is determined by the signal of adder 2. With the end of the clock pulse, adder 2 is closed and the trigger 1.1 is latched and continues to hold the signal unchanged.

Further, the whole process is repeated.

Thus, register 1 with adder 2 in the feedback circuit generates a pseudo-random sequence with a period of t-1. At the same time, the delay time of the signal arriving at the input of the discharge 1.2 from the outputs

bits l.i and l.m, equal to 2

those. generator is in range

clock frequency from O to F.

NVOKC

 1 / t

The proposed implementation of the first bit of the shift register and modulo two adder and the introduction of new connections distinguish the claimed generator from the classical one favorably, since they allow to exclude the delay time in the first bit, as a result, the generator achieves the maximum possible speed, which increases the its application.

Claims (2)

1. Harvey. Improving the performance of the generator M-sequence through the delay line. Electronics, 1975, 24. 2. Yakovlev V. V., Fedorov R. F. Stochastic Computational Calculations. L., Mechanical Engineering, 1974, with. 247 (prototype).